init: add parentheses around #define with an expression
This commit is contained in:
parent
d20e8c763b
commit
91cae335e5
|
@ -707,7 +707,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
|
||||||
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
|
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
|
||||||
|
|
||||||
# Define number of modules/delays/bitslips
|
# Define number of modules/delays/bitslips
|
||||||
r += "#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8\n"
|
r += "#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)\n"
|
||||||
if phytype in ["USDDRPHY", "USPDDRPHY"]:
|
if phytype in ["USDDRPHY", "USPDDRPHY"]:
|
||||||
r += "#define SDRAM_PHY_DELAYS 512\n"
|
r += "#define SDRAM_PHY_DELAYS 512\n"
|
||||||
r += "#define SDRAM_PHY_BITSLIPS 8\n"
|
r += "#define SDRAM_PHY_BITSLIPS 8\n"
|
||||||
|
|
|
@ -28,7 +28,7 @@
|
||||||
#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
|
#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
|
||||||
#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
|
#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
|
||||||
#define SDRAM_PHY_READ_LEVELING_CAPABLE
|
#define SDRAM_PHY_READ_LEVELING_CAPABLE
|
||||||
#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
|
#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
|
||||||
#define SDRAM_PHY_DELAYS 32
|
#define SDRAM_PHY_DELAYS 32
|
||||||
#define SDRAM_PHY_BITSLIPS 8
|
#define SDRAM_PHY_BITSLIPS 8
|
||||||
|
|
||||||
|
|
|
@ -27,7 +27,7 @@
|
||||||
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
|
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
|
||||||
#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
|
#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
|
||||||
#define SDRAM_PHY_READ_LEVELING_CAPABLE
|
#define SDRAM_PHY_READ_LEVELING_CAPABLE
|
||||||
#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
|
#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
|
||||||
#define SDRAM_PHY_DELAYS 512
|
#define SDRAM_PHY_DELAYS 512
|
||||||
#define SDRAM_PHY_BITSLIPS 8
|
#define SDRAM_PHY_BITSLIPS 8
|
||||||
|
|
||||||
|
|
|
@ -23,7 +23,7 @@
|
||||||
#define SDRAM_PHY_CWL 2
|
#define SDRAM_PHY_CWL 2
|
||||||
#define SDRAM_PHY_RDPHASE 0
|
#define SDRAM_PHY_RDPHASE 0
|
||||||
#define SDRAM_PHY_WRPHASE 0
|
#define SDRAM_PHY_WRPHASE 0
|
||||||
#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
|
#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
|
||||||
|
|
||||||
void cdelay(int i);
|
void cdelay(int i);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue