frontend/bist: simplify and fix CDC using AsyncFIFO.
This commit is contained in:
Florent Kermarrec
parent
378c4419c1
commit
92e34d4d37
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@ -8,10 +8,8 @@ from functools import reduce
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from operator import xor
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from operator import xor
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from migen import *
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import PulseSynchronizer
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from migen.genlib.cdc import BusSynchronizer
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from litex.soc.interconnect import stream
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr import *
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from litedram.common import LiteDRAMNativePort
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from litedram.common import LiteDRAMNativePort
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@ -339,49 +337,63 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
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self.submodules += core
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self.submodules += core
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if clock_domain != "sys":
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if clock_domain != "sys":
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reset_sync = PulseSynchronizer("sys", clock_domain)
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control_layout = [
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start_sync = PulseSynchronizer("sys", clock_domain)
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("reset", 1),
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self.submodules += reset_sync, start_sync
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("start", 1),
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self.comb += [
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("base", awidth),
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reset_sync.i.eq(self.reset.re),
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("end", awidth),
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core.reset.eq(reset_sync.o),
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("length", awidth),
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("random_data", 1),
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start_sync.i.eq(self.start.re),
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("random_addr", 1),
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core.start.eq(start_sync.o)
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]
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]
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status_layout = [
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done_sync = BusSynchronizer(1, clock_domain, "sys")
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("done", 1),
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self.submodules += done_sync
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("ticks", 32),
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self.comb += [
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done_sync.i.eq(core.done),
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self.done.status.eq(done_sync.o)
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]
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]
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control_cdc = stream.AsyncFIFO(control_layout)
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base_sync = BusSynchronizer(awidth, "sys", clock_domain)
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control_cdc = ClockDomainsRenamer({"write" : "sys", "read": clock_domain})(control_cdc)
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end_sync = BusSynchronizer(awidth, "sys", clock_domain)
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status_cdc = stream.AsyncFIFO(status_layout)
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length_sync = BusSynchronizer(awidth, "sys", clock_domain)
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status_cdc = ClockDomainsRenamer({"write" : clock_domain, "read": "sys"})(status_cdc)
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self.submodules += base_sync, end_sync, length_sync
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self.submodules += control_cdc, status_cdc
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# Control CDC In
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self.comb += [
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self.comb += [
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base_sync.i.eq(self.base.storage),
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control_cdc.sink.valid.eq(self.reset.re | self.start.re),
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core.base.eq(base_sync.o),
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control_cdc.sink.reset.eq(self.reset.re),
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control_cdc.sink.start.eq(self.start.re),
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end_sync.i.eq(self.end.storage),
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control_cdc.sink.base.eq(self.base.storage),
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core.end.eq(end_sync.o),
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control_cdc.sink.end.eq(self.end.storage),
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control_cdc.sink.length.eq(self.length.storage),
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length_sync.i.eq(self.length.storage),
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control_cdc.sink.random_data.eq(self.random.fields.data),
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core.length.eq(length_sync.o)
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control_cdc.sink.random_addr.eq(self.random.fields.addr),
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]
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]
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# Control CDC Out
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self.specials += [
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MultiReg(self.random.fields.data, core.random_data, clock_domain),
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MultiReg(self.random.fields.addr, core.random_addr, clock_domain),
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]
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ticks_sync = BusSynchronizer(32, clock_domain, "sys")
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self.submodules += ticks_sync
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self.comb += [
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self.comb += [
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ticks_sync.i.eq(core.ticks),
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control_cdc.source.ready.eq(1),
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self.ticks.status.eq(ticks_sync.o)
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core.reset.eq(control_cdc.source.valid & control_cdc.source.reset),
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core.start.eq(control_cdc.source.valid & control_cdc.source.start),
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]
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self.sync += [
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If(control_cdc.source.valid,
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core.base.eq(control_cdc.source.base),
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core.end.eq(control_cdc.source.end),
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core.length.eq(control_cdc.source.length),
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core.random_data.eq(control_cdc.source.random_data),
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core.random_addr.eq(control_cdc.source.random_addr),
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)
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]
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# Status CDC In
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self.comb += [
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status_cdc.sink.valid.eq(1),
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status_cdc.sink.done.eq(core.done),
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status_cdc.sink.ticks.eq(core.ticks),
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]
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# Status CDC Out
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self.comb += status_cdc.source.ready.eq(1)
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self.sync += [
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If(status_cdc.source.valid,
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self.done.status.eq(status_cdc.source.done),
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self.ticks.status.eq(status_cdc.source.ticks),
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)
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]
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]
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else:
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else:
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self.comb += [
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self.comb += [
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@ -671,56 +683,66 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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self.submodules += core
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self.submodules += core
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if clock_domain != "sys":
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if clock_domain != "sys":
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reset_sync = PulseSynchronizer("sys", clock_domain)
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control_layout = [
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start_sync = PulseSynchronizer("sys", clock_domain)
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("reset", 1),
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self.submodules += reset_sync, start_sync
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("start", 1),
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self.comb += [
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("base", awidth),
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reset_sync.i.eq(self.reset.re),
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("end", awidth),
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core.reset.eq(reset_sync.o),
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("length", awidth),
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("random_data", 1),
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start_sync.i.eq(self.start.re),
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("random_addr", 1),
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core.start.eq(start_sync.o)
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]
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]
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status_layout = [
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done_sync = BusSynchronizer(1, clock_domain, "sys")
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("done", 1),
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self.submodules += done_sync
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("ticks", 32),
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self.comb += [
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("errors", 32),
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done_sync.i.eq(core.done),
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self.done.status.eq(done_sync.o)
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]
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]
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control_cdc = stream.AsyncFIFO(control_layout)
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base_sync = BusSynchronizer(awidth, "sys", clock_domain)
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control_cdc = ClockDomainsRenamer({"write" : "sys", "read": clock_domain})(control_cdc)
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end_sync = BusSynchronizer(awidth, "sys", clock_domain)
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status_cdc = stream.AsyncFIFO(status_layout)
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length_sync = BusSynchronizer(awidth, "sys", clock_domain)
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status_cdc = ClockDomainsRenamer({"write" : clock_domain, "read": "sys"})(status_cdc)
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self.submodules += base_sync, end_sync, length_sync
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self.submodules += control_cdc, status_cdc
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# Control CDC In
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self.comb += [
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self.comb += [
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base_sync.i.eq(self.base.storage),
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control_cdc.sink.valid.eq(self.reset.re | self.start.re),
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core.base.eq(base_sync.o),
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control_cdc.sink.reset.eq(self.reset.re),
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control_cdc.sink.start.eq(self.start.re),
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end_sync.i.eq(self.end.storage),
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control_cdc.sink.base.eq(self.base.storage),
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core.end.eq(end_sync.o),
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control_cdc.sink.end.eq(self.end.storage),
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control_cdc.sink.length.eq(self.length.storage),
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length_sync.i.eq(self.length.storage),
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control_cdc.sink.random_data.eq(self.random.fields.data),
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core.length.eq(length_sync.o)
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control_cdc.sink.random_addr.eq(self.random.fields.addr),
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]
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]
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# Control CDC Out
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self.specials += [
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MultiReg(self.random.fields.data, core.random_data, clock_domain),
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MultiReg(self.random.fields.addr, core.random_addr, clock_domain),
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]
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ticks_sync = BusSynchronizer(32, clock_domain, "sys")
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self.submodules += ticks_sync
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self.comb += [
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self.comb += [
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ticks_sync.i.eq(core.ticks),
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control_cdc.source.ready.eq(1),
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self.ticks.status.eq(ticks_sync.o)
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core.reset.eq(control_cdc.source.valid & control_cdc.source.reset),
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core.start.eq(control_cdc.source.valid & control_cdc.source.start),
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]
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]
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self.sync += [
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errors_sync = BusSynchronizer(32, clock_domain, "sys")
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If(control_cdc.source.valid,
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self.submodules += errors_sync
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core.base.eq(control_cdc.source.base),
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core.end.eq(control_cdc.source.end),
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core.length.eq(control_cdc.source.length),
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core.random_data.eq(control_cdc.source.random_data),
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core.random_addr.eq(control_cdc.source.random_addr),
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)
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]
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# Status CDC In
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self.comb += [
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self.comb += [
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errors_sync.i.eq(core.errors),
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status_cdc.sink.valid.eq(1),
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self.errors.status.eq(errors_sync.o)
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status_cdc.sink.done.eq(core.done),
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status_cdc.sink.ticks.eq(core.ticks),
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status_cdc.sink.errors.eq(core.errors),
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]
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# Status CDC Out
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self.comb += status_cdc.source.ready.eq(1)
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self.sync += [
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If(status_cdc.source.valid,
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self.done.status.eq(status_cdc.source.done),
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self.ticks.status.eq(status_cdc.source.ticks),
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self.errors.status.eq(status_cdc.source.errors),
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)
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]
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]
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else:
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else:
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self.comb += [
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self.comb += [
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@ -733,5 +755,5 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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core.random_data.eq(self.random.fields.data),
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core.random_data.eq(self.random.fields.data),
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core.random_addr.eq(self.random.fields.addr),
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core.random_addr.eq(self.random.fields.addr),
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self.ticks.status.eq(core.ticks),
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self.ticks.status.eq(core.ticks),
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self.errors.status.eq(core.errors)
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self.errors.status.eq(core.errors),
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]
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]
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