Merge pull request #178 from antmicro/jboc/unit-tests-crossbar
Add litedram.core.crossbar tests
This commit is contained in:
enjoy-digital
GitHub
commit
969943e4c5
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@ -36,6 +36,58 @@ def timeout_generator(ticks):
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raise TimeoutError("Timeout after %d ticks" % ticks)
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class NativePortDriver:
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"""Generates sequences for reading/writing to LiteDRAMNativePort
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The write/read versions with wait_data=False are a cheap way to perform
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burst during which the port is being held locked, but this way all the
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data is being lost (would require separate coroutine to handle data).
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"""
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def __init__(self, port):
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self.port = port
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def read(self, address, wait_data=True):
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yield self.port.cmd.valid.eq(1)
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yield self.port.cmd.we.eq(0)
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yield self.port.cmd.addr.eq(address)
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yield
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while (yield self.port.cmd.ready) == 0:
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yield
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yield self.port.cmd.valid.eq(0)
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yield
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if wait_data:
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while (yield self.port.rdata.valid) == 0:
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yield
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data = (yield self.port.rdata.data)
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yield self.port.rdata.ready.eq(1)
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yield
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yield self.port.rdata.ready.eq(0)
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yield
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return data
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else:
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yield self.port.rdata.ready.eq(1)
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def write(self, address, data, we=None, wait_data=True):
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if we is None:
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we = 2**self.port.wdata.we.nbits - 1
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yield self.port.cmd.valid.eq(1)
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yield self.port.cmd.we.eq(1)
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yield self.port.cmd.addr.eq(address)
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yield
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while (yield self.port.cmd.ready) == 0:
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yield
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yield self.port.cmd.valid.eq(0)
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yield self.port.wdata.valid.eq(1)
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yield self.port.wdata.data.eq(data)
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yield self.port.wdata.we.eq(we)
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yield
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if wait_data:
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while (yield self.port.wdata.ready) == 0:
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yield
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yield self.port.wdata.valid.eq(0)
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yield
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class CmdRequestRWDriver:
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"""Simple driver for Endpoint(cmd_request_rw_layout())"""
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def __init__(self, req, i=0, ep_layout=True, rw_layout=True):
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@ -256,7 +256,7 @@ class TestBankMachine(unittest.TestCase):
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def test_burst_no_request_lost(self):
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# Verify that no request is lost in fast bursts of requests regardless of cmd_buffer_depth
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for cmd_buffer_depth in [8]:
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for cmd_buffer_depth in [8, 1, 0]:
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settings = dict(cmd_buffer_depth=cmd_buffer_depth)
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with self.subTest(**settings):
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dut = BankMachineDUT(1, controller_settings=settings)
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@ -0,0 +1,513 @@
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import random
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import unittest
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import functools
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import itertools
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from collections import namedtuple, defaultdict
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from migen import *
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from litedram.common import *
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from litedram.core.crossbar import LiteDRAMCrossbar
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from test.common import timeout_generator, NativePortDriver
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class ControllerStub:
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"""Simplified simulation of LiteDRAMController as seen by LiteDRAMCrossbar
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This is a simplified implementation of LiteDRAMController suitable for
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testing the crossbar. It consisits of bankmachine handlers that try to mimic
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behaviour of real BankMachines. They also simulate data transmission by
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scheduling it to appear on data interface (data_handler sets it).
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"""
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W = namedtuple("WriteData", ["bank", "addr", "data", "we"])
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R = namedtuple("ReadData", ["bank", "addr", "data"])
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WaitingData = namedtuple("WaitingData", ["delay", "data"])
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def __init__(self, controller_interface, write_latency, read_latency, cmd_delay=None):
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self.interface = controller_interface
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self.write_latency = write_latency
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self.read_latency = read_latency
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self.data = [] # data registered on datapath (W/R)
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self._waiting = [] # data waiting to be set on datapath
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# incremental generator of artificial read data
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self._read_data = itertools.count(0x10)
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# simulated dealy of command processing, by default just constant
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self._cmd_delay = cmd_delay or (lambda: 6)
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# minimal logic required so that no two banks will become ready at the same moment
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self._multiplexer_lock = None
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def generators(self):
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bank_handlers = [self.bankmachine_handler(bn) for bn in range(self.interface.nbanks)]
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return [self.data_handler(), *bank_handlers]
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@passive
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def data_handler(self):
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# Responsible for passing data over datapath with requested latency
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while True:
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# Examine requests to find if there is any for that cycle
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available = [w for w in self._waiting if w.delay == 0]
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# Make sure that it is never the case that we have more then 1
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# operation of the same type
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type_counts = defaultdict(int)
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for a in available:
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type_counts[type(a.data)] += 1
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for t, count in type_counts.items():
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assert count == 1, \
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"%d data operations of type %s at the same time!" % (count, t.__name__)
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for a in available:
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# Remove it from the list and get the data
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current = self._waiting.pop(self._waiting.index(a)).data
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# If this was a write, then fill it with data from this cycle
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if isinstance(current, self.W):
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current = current._replace(
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data=(yield self.interface.wdata),
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we=(yield self.interface.wdata_we),
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)
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# If this was a read, then assert the data now
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elif isinstance(current, self.R):
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yield self.interface.rdata.eq(current.data)
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else:
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raise TypeError(current)
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# Add it to the data that appeared on the datapath
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self.data.append(current)
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# Advance simulation time by 1 cycle
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for i, w in enumerate(self._waiting):
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self._waiting[i] = w._replace(delay=w.delay - 1)
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yield
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@passive
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def bankmachine_handler(self, n):
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# Simplified simulation of a bank machine.
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# Uses a single buffer (no input fifo). Generates random read data.
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bank = getattr(self.interface, "bank%d" % n)
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while True:
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# Wait for a valid bank command
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while not (yield bank.valid):
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# The lock is being held as long as there is a valid command
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# in the buffer or there is a valid command on the interface.
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# As at this point we have nothing in the buffer, we unlock
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# the lock only if the command on the interface is not valid.
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yield bank.lock.eq(0)
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yield
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# Latch the command to the internal buffer
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cmd_addr = (yield bank.addr)
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cmd_we = (yield bank.we)
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# Lock the buffer as soon as command is valid on the interface.
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# We do this 1 cycle after we see the command, but BankMachine
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# also has latency, because cmd_buffer_lookahead.source must
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# become valid.
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yield bank.lock.eq(1)
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yield bank.ready.eq(1)
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yield
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yield bank.ready.eq(0)
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# Simulate that we are processing the command
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for _ in range(self._cmd_delay()):
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yield
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# Avoid situation that can happen due to the lack of multiplexer,
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# where more than one bank would send data at the same moment
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while self._multiplexer_lock is not None:
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yield
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self._multiplexer_lock = n
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yield
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# After READ/WRITE has been issued, this is signalized by using
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# rdata_valid/wdata_ready. The actual data will appear with latency.
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if cmd_we: # WRITE
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yield bank.wdata_ready.eq(1)
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yield
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yield bank.wdata_ready.eq(0)
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# Send a request to the data_handler, it will check what
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# has been sent from the crossbar port.
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wdata = self.W(bank=n, addr=cmd_addr,
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data=None, we=None) # to be filled in callback
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self._waiting.append(self.WaitingData(data=wdata, delay=self.write_latency))
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else: # READ
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yield bank.rdata_valid.eq(1)
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yield
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yield bank.rdata_valid.eq(0)
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# Send a request with "data from memory" to the data_handler
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rdata = self.R(bank=n, addr=cmd_addr, data=next(self._read_data))
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# Decrease latecy, as data_handler sets data with 1 cycle delay
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self._waiting.append(self.WaitingData(data=rdata, delay=self.read_latency - 1))
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# At this point cmd_buffer.source.ready has been activated and the
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# command in internal buffer has been discarded. The lock will be
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self._multiplexer_lock = None
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# removed in next loop if there is no other command pending.
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yield
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class CrossbarDUT(Module):
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default_controller_settings = dict(
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cmd_buffer_depth=8,
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address_mapping="ROW_BANK_COL",
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)
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default_phy_settings = dict(
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cwl=2,
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nphases=2,
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nranks=1,
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memtype="DDR2",
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dfi_databits=2*16,
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read_latency=5,
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write_latency=1,
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)
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default_geom_settings = dict(
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bankbits=3,
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rowbits=13,
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colbits=10,
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)
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def __init__(self, controller_settings=None, phy_settings=None, geom_settings=None):
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# update settings if provided
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def updated(settings, update):
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copy = settings.copy()
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copy.update(update or {})
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return copy
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controller_settings = updated(self.default_controller_settings, controller_settings)
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phy_settings = updated(self.default_phy_settings, phy_settings)
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geom_settings = updated(self.default_geom_settings, geom_settings)
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class SimpleSettings(Settings):
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def __init__(self, **kwargs):
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self.set_attributes(kwargs)
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settings = SimpleSettings(**controller_settings)
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settings.phy = SimpleSettings(**phy_settings)
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settings.geom = SimpleSettings(**geom_settings)
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self.settings = settings
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self.address_align = log2_int(burst_lengths[settings.phy.memtype])
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self.interface = LiteDRAMInterface(self.address_align, settings)
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self.submodules.crossbar = LiteDRAMCrossbar(self.interface)
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def addr_port(self, bank, row, col):
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# construct an address the way port master would do it
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assert self.settings.address_mapping == "ROW_BANK_COL"
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aa = self.address_align
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cb = self.settings.geom.colbits
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rb = self.settings.geom.rowbits
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bb = self.settings.geom.bankbits
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col = (col & (2**cb - 1)) >> aa
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bank = (bank & (2**bb - 1)) << (cb - aa)
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row = (row & (2**rb - 1)) << (cb + bb - aa)
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return row | bank | col
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def addr_iface(self, row, col):
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# construct address the way bankmachine should receive it
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aa = self.address_align
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cb = self.settings.geom.colbits
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rb = self.settings.geom.rowbits
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col = (col & (2**cb - 1)) >> aa
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row = (row & (2**rb - 1)) << (cb - aa)
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return row | col
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class TestCrossbar(unittest.TestCase):
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W = ControllerStub.W
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R = ControllerStub.R
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def test_init(self):
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dut = CrossbarDUT()
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dut.crossbar.get_port()
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dut.finalize()
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def crossbar_test(self, dut, generators, timeout=100, **kwargs):
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# Runs simulation with a controller stub (passive generators) and user generators
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if not isinstance(generators, list):
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generators = [generators]
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controller = ControllerStub(dut.interface,
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write_latency=dut.settings.phy.write_latency,
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read_latency=dut.settings.phy.read_latency,
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**kwargs)
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generators += [*controller.generators(), timeout_generator(timeout)]
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run_simulation(dut, generators)
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return controller.data
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def test_available_address_mappings(self):
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# Check that the only supported address mapping is ROW_BANK_COL
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# (if we start supporting new mappings, then update these tests to also
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# test these other mappings)
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def finalize_crossbar(mapping):
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dut = CrossbarDUT(controller_settings=dict(address_mapping=mapping))
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dut.crossbar.get_port()
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dut.crossbar.finalize()
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for mapping in ["ROW_BANK_COL", "BANK_ROW_COL"]:
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if mapping in ["ROW_BANK_COL"]:
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finalize_crossbar(mapping)
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else:
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with self.assertRaises(KeyError):
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finalize_crossbar(mapping)
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def test_address_mappings(self):
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# Verify that address is translated correctly
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reads = []
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def producer(dut, port):
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driver = NativePortDriver(port)
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for t in transfers:
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addr = dut.addr_port(bank=t["bank"], row=t["row"], col=t["col"])
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if t["rw"] == self.W:
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yield from driver.write(addr, data=t["data"], we=t.get("we", None))
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elif t["rw"] == self.R:
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data = (yield from driver.read(addr))
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reads.append(data)
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else:
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raise TypeError(t["rw"])
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geom_settings = dict(colbits=10, rowbits=13, bankbits=2)
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dut = CrossbarDUT(geom_settings=geom_settings)
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port = dut.crossbar.get_port()
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transfers = [
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dict(rw=self.W, bank=2, row=0x30, col=0x03, data=0x20),
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dict(rw=self.W, bank=3, row=0x30, col=0x03, data=0x21),
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dict(rw=self.W, bank=2, row=0xab, col=0x03, data=0x22),
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dict(rw=self.W, bank=2, row=0x30, col=0x13, data=0x23),
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dict(rw=self.R, bank=1, row=0x10, col=0x99),
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dict(rw=self.R, bank=0, row=0x10, col=0x99),
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dict(rw=self.R, bank=1, row=0xcd, col=0x99),
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dict(rw=self.R, bank=1, row=0x10, col=0x77),
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]
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expected = []
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for i, t in enumerate(transfers):
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cls = t["rw"]
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addr = dut.addr_iface(row=t["row"], col=t["col"])
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if cls == self.W:
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kwargs = dict(data=t["data"], we=0xff)
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elif cls == self.R:
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kwargs = dict(data=0x10 + i)
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return cls(bank=t["bank"], addr=addr, **kwargs)
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data = self.crossbar_test(dut, producer(port))
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self.assertEqual(data, expected)
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def test_arbitration(self):
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# Create multiple masters that write to the same bank at the same time
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# and verify that all the requests have been sent correctly.
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def producer(dut, port, num):
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driver = NativePortDriver(port)
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addr = dut.addr_port(bank=3, row=0x10 + num, col=0x20 + num)
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yield from driver.write(addr, data=0x30 + num)
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dut = CrossbarDUT()
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ports = [dut.crossbar.get_port() for _ in range(4)]
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masters = [producer(dut, port, i) for i, port in enumerate(ports)]
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data = self.crossbar_test(dut, masters)
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expected = {
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self.W(bank=3, addr=dut.addr_iface(row=0x10, col=0x20), data=0x30, we=0xff),
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self.W(bank=3, addr=dut.addr_iface(row=0x11, col=0x21), data=0x31, we=0xff),
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self.W(bank=3, addr=dut.addr_iface(row=0x12, col=0x22), data=0x32, we=0xff),
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self.W(bank=3, addr=dut.addr_iface(row=0x13, col=0x23), data=0x33, we=0xff),
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}
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self.assertEqual(set(data), expected)
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def test_lock_write(self):
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# Verify that the locking mechanism works
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# Create a situation when one master A wants to write to banks 0 then 1,
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# but master B is continuously writing to bank 1 (bank is locked) so
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# that master A is blocked. We use wait_data=False because we are only
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# concerned about sending commands fast enough for the lock to be held
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# continuously.
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def master_a(dut, port):
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driver = NativePortDriver(port)
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adr = functools.partial(dut.addr_port, row=1, col=1)
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write = functools.partial(driver.write, wait_data=False)
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yield from write(adr(bank=0), data=0x10)
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yield from write(adr(bank=1), data=0x11)
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yield from write(adr(bank=0), data=0x12, wait_data=True)
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def master_b(dut, port):
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driver = NativePortDriver(port)
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adr = functools.partial(dut.addr_port, row=2, col=2)
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write = functools.partial(driver.write, wait_data=False)
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yield from write(adr(bank=1), data=0x20)
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yield from write(adr(bank=1), data=0x21)
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yield from write(adr(bank=1), data=0x22)
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yield from write(adr(bank=1), data=0x23)
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yield from write(adr(bank=1), data=0x24)
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dut = CrossbarDUT()
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ports = [dut.crossbar.get_port() for _ in range(2)]
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data = self.crossbar_test(dut, [master_a(dut, ports[0]), master_b(dut, ports[1])])
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expected = [
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self.W(bank=0, addr=dut.addr_iface(row=1, col=1), data=0x10, we=0xff), # A
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self.W(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x20, we=0xff), # B
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self.W(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x21, we=0xff), # B
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self.W(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x22, we=0xff), # B
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self.W(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x23, we=0xff), # B
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self.W(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x24, we=0xff), # B
|
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self.W(bank=1, addr=dut.addr_iface(row=1, col=1), data=0x11, we=0xff), # A
|
||||
self.W(bank=0, addr=dut.addr_iface(row=1, col=1), data=0x12, we=0xff), # A
|
||||
]
|
||||
self.assertEqual(data, expected)
|
||||
|
||||
def test_lock_read(self):
|
||||
# Verify that the locking mechanism works
|
||||
def master_a(dut, port):
|
||||
driver = NativePortDriver(port)
|
||||
adr = functools.partial(dut.addr_port, row=1, col=1)
|
||||
read = functools.partial(driver.read, wait_data=False)
|
||||
yield from read(adr(bank=0))
|
||||
yield from read(adr(bank=1))
|
||||
yield from read(adr(bank=0))
|
||||
# wait for read data to show up
|
||||
for _ in range(16):
|
||||
yield
|
||||
|
||||
def master_b(dut, port):
|
||||
driver = NativePortDriver(port)
|
||||
adr = functools.partial(dut.addr_port, row=2, col=2)
|
||||
read = functools.partial(driver.read, wait_data=False)
|
||||
yield from read(adr(bank=1))
|
||||
yield from read(adr(bank=1))
|
||||
yield from read(adr(bank=1))
|
||||
yield from read(adr(bank=1))
|
||||
yield from read(adr(bank=1))
|
||||
|
||||
dut = CrossbarDUT()
|
||||
ports = [dut.crossbar.get_port() for _ in range(2)]
|
||||
data = self.crossbar_test(dut, [master_a(dut, ports[0]), master_b(dut, ports[1])])
|
||||
expected = [
|
||||
self.R(bank=0, addr=dut.addr_iface(row=1, col=1), data=0x10), # A
|
||||
self.R(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x11), # B
|
||||
self.R(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x12), # B
|
||||
self.R(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x13), # B
|
||||
self.R(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x14), # B
|
||||
self.R(bank=1, addr=dut.addr_iface(row=2, col=2), data=0x15), # B
|
||||
self.R(bank=1, addr=dut.addr_iface(row=1, col=1), data=0x16), # A
|
||||
self.R(bank=0, addr=dut.addr_iface(row=1, col=1), data=0x17), # A
|
||||
]
|
||||
self.assertEqual(data, expected)
|
||||
|
||||
def crossbar_stress_test(self, dut, ports, n_banks, n_ops, clocks=None):
|
||||
# Runs simulation with multiple masters writing and reading to multiple banks
|
||||
controller = ControllerStub(dut.interface,
|
||||
write_latency=dut.settings.phy.write_latency,
|
||||
read_latency=dut.settings.phy.read_latency)
|
||||
# Store data produced per master
|
||||
produced = defaultdict(list)
|
||||
prng = random.Random(42)
|
||||
|
||||
def master(dut, port, num):
|
||||
# Choose operation types based on port mode
|
||||
ops_choice = {
|
||||
"both": ["w", "r"],
|
||||
"write": ["w"],
|
||||
"read": ["r"],
|
||||
}[port.mode]
|
||||
driver = NativePortDriver(port)
|
||||
|
||||
for i in range(n_ops):
|
||||
bank = prng.randrange(n_banks)
|
||||
# We will later distinguish data by its row address
|
||||
row = num
|
||||
col = 0x20 * num + i
|
||||
addr = dut.addr_port(bank=bank, row=row, col=col)
|
||||
addr_iface = dut.addr_iface(row=row, col=col)
|
||||
if prng.choice(ops_choice) == "w":
|
||||
yield from driver.write(addr, data=i)
|
||||
produced[num].append(self.W(bank, addr_iface, data=i, we=0xff))
|
||||
else:
|
||||
yield from driver.read(addr)
|
||||
produced[num].append(self.R(bank, addr_iface, data=None))
|
||||
|
||||
for _ in range(8):
|
||||
yield
|
||||
|
||||
generators = defaultdict(list)
|
||||
for i, port in enumerate(ports):
|
||||
generators[port.clock_domain].append(master(dut, port, i))
|
||||
generators["sys"] += controller.generators()
|
||||
generators["sys"].append(timeout_generator(80 * n_ops))
|
||||
|
||||
sim_kwargs = {}
|
||||
if clocks is not None:
|
||||
sim_kwargs["clocks"] = clocks
|
||||
run_simulation(dut, generators, **sim_kwargs)
|
||||
|
||||
# split controller data by master, as this is what we want to compare
|
||||
consumed = defaultdict(list)
|
||||
for data in controller.data:
|
||||
master = data.addr >> (dut.settings.geom.colbits - dut.address_align)
|
||||
if isinstance(data, self.R):
|
||||
# master couldn't know the data when it was sending
|
||||
data = data._replace(data=None)
|
||||
consumed[master].append(data)
|
||||
|
||||
return produced, consumed, controller.data
|
||||
|
||||
def test_stress(self):
|
||||
# Test communication in complex scenarion
|
||||
dut = CrossbarDUT()
|
||||
ports = [dut.crossbar.get_port() for _ in range(8)]
|
||||
produced, consumed, consumed_all = self.crossbar_stress_test(dut, ports, n_banks=4, n_ops=8)
|
||||
for master in produced.keys():
|
||||
self.assertEqual(consumed[master], produced[master], msg="master = %d" % master)
|
||||
|
||||
def test_stress_single_bank(self):
|
||||
# Test communication in complex scenarion
|
||||
dut = CrossbarDUT()
|
||||
ports = [dut.crossbar.get_port() for _ in range(4)]
|
||||
produced, consumed, consumed_all = self.crossbar_stress_test(dut, ports, n_banks=1, n_ops=8)
|
||||
for master in produced.keys():
|
||||
self.assertEqual(consumed[master], produced[master], msg="master = %d" % master)
|
||||
|
||||
def test_stress_single_master(self):
|
||||
# Test communication in complex scenarion
|
||||
dut = CrossbarDUT()
|
||||
ports = [dut.crossbar.get_port() for _ in range(1)]
|
||||
produced, consumed, consumed_all = self.crossbar_stress_test(dut, ports, n_banks=4, n_ops=8)
|
||||
for master in produced.keys():
|
||||
self.assertEqual(consumed[master], produced[master], msg="master = %d" % master)
|
||||
|
||||
def test_port_cdc(self):
|
||||
# Verify that correct clock domain is being used
|
||||
dut = CrossbarDUT()
|
||||
port = dut.crossbar.get_port(clock_domain="other")
|
||||
self.assertEqual(port.clock_domain, "other")
|
||||
|
||||
def test_stress_cdc(self):
|
||||
# Verify communication when ports are in different clock domains
|
||||
dut = CrossbarDUT()
|
||||
clocks = {
|
||||
"sys": 10,
|
||||
"clk1": (7, 4),
|
||||
"clk2": 12,
|
||||
}
|
||||
master_clocks = ["sys", "clk1", "clk2"]
|
||||
ports = [dut.crossbar.get_port(clock_domain=clk) for clk in master_clocks]
|
||||
produced, consumed, consumed_all = self.crossbar_stress_test(
|
||||
dut, ports, n_banks=4, n_ops=6, clocks=clocks)
|
||||
for master in produced.keys():
|
||||
self.assertEqual(consumed[master], produced[master], msg="master = %d" % master)
|
||||
|
||||
def test_port_mode(self):
|
||||
# Verify that ports in different modes can be requested
|
||||
dut = CrossbarDUT()
|
||||
for mode in ["both", "write", "read"]:
|
||||
port = dut.crossbar.get_port(mode=mode)
|
||||
self.assertEqual(port.mode, mode)
|
||||
|
||||
# NOTE: Stress testing with different data widths would require complicating
|
||||
# the logic a lot to support registering data comming in multiple words (in
|
||||
# data_handler), address shifting and recreation of packets. Because of this,
|
||||
# and because data width converters are tested separately in test_adaptation,
|
||||
# here we only test if ports report correct data widths.
|
||||
def test_port_data_width_conversion(self):
|
||||
# Verify that correct port data widths are being used
|
||||
dut = CrossbarDUT()
|
||||
dw = dut.interface.data_width
|
||||
data_widths = [dw*2, dw, dw//2]
|
||||
modes = ["both", "write", "read"]
|
||||
for mode, data_width in itertools.product(modes, data_widths):
|
||||
with self.subTest(mode=mode, data_width=data_width):
|
||||
# up conversion is supported only for single direction ports
|
||||
if mode == "both" and data_width < dut.interface.data_width:
|
||||
with self.assertRaises(NotImplementedError):
|
||||
dut.crossbar.get_port(mode=mode, data_width=data_width)
|
||||
else:
|
||||
port = dut.crossbar.get_port(mode=mode, data_width=data_width)
|
||||
self.assertEqual(port.data_width, data_width)
|
||||
Loading…
Reference in New Issue