common/BitSlip: use reset_less on intermediate signal.

2020-04-06 11:59:34 +02:00 · 2020-04-06 11:59:34 +02:00 · 96b273c523
parent b06e946d09
commit 96b273c523
1 changed files with 1 additions and 1 deletions
--- a/litedram/common.py
+++ b/litedram/common.py
@ -93,7 +93,7 @@ class BitSlip(Module):

        # # #

-        r = Signal(2*dw)
+        r = Signal(2*dw, reset_less=True)
        self.sync += r.eq(Cat(r[dw:], self.i))
        cases = {}
        for i in range(dw):