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litedram/init: pass write latency calibration capability to software.

This commit is contained in:
Florent Kermarrec 2020-10-12 15:50:35 +02:00
parent a1e8bcb53c
commit 97b4029be7
1 changed files with 1 additions and 0 deletions
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litedram/init.py
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@ -508,6 +508,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
if phytype in ["USDDRPHY", "USPDDRPHY"]:
r += "#define SDRAM_PHY_WRITE_LEVELING_REINIT\n"
if phytype in ["USDDRPHY", "USPDDRPHY", "A7DDRPHY", "K7DDRPHY", "V7DDRPHY", "ECP5DDRPHY"]:
r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
# Define number of modules/delays/bitslips