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init: enable DQ-DQS training for LPDDR4 PHYs with output delays

This commit is contained in:
Jędrzej Boczar 2021-04-16 15:12:44 +02:00
parent 26c9f82c1b
commit 98f2f24e20
1 changed files with 2 additions and 0 deletions
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2
litedram/init.py
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@ -690,6 +690,8 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
'K7LPDDR4PHY', 'V7LPDDR4PHY']:
r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
if phytype in ['K7LPDDR4PHY', 'V7LPDDR4PHY']:
r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
if phytype in ["ECP5DDRPHY"]:
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
if phytype in ["LPDDR4SIMPHY"]: