rename bus to common

This commit is contained in:
Florent Kermarrec 2016-04-29 17:15:06 +02:00
parent 077043e310
commit 997c1ce707
3 changed files with 3 additions and 4 deletions

View file

@ -2,7 +2,6 @@ from functools import reduce
from operator import or_
from litex.gen import *
from litex.gen.genlib.record import *
class Interface(Record):

View file

@ -1,7 +1,7 @@
from litex.gen import *
from litedram.phy import dfi
from litedram import bus
from litedram import common
from litedram.core.refresher import *
from litedram.core.bankmachine import *
from litedram.core.multiplexer import *
@ -30,7 +30,7 @@ class LiteDRAMController(Module):
geom_settings.bankbits,
phy_settings.dfi_databits,
phy_settings.nphases)
self.lasmic = bus.Interface(
self.lasmic = common.Interface(
aw=geom_settings.rowbits + geom_settings.colbits - address_align,
dw=phy_settings.dfi_databits*phy_settings.nphases,
nbanks=2**geom_settings.bankbits,

View file

@ -4,7 +4,7 @@ from operator import or_
from litex.gen import *
from litex.gen.genlib import roundrobin
from litedram.bus import *
from litedram.common import *
class LiteDRAMCrossbar(Module):