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rename bus to common
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parent
077043e310
commit
997c1ce707
3 changed files with 3 additions and 4 deletions
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@ -2,7 +2,6 @@ from functools import reduce
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from operator import or_
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from litex.gen import *
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from litex.gen.genlib.record import *
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class Interface(Record):
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@ -1,7 +1,7 @@
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from litex.gen import *
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from litedram.phy import dfi
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from litedram import bus
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from litedram import common
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from litedram.core.refresher import *
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from litedram.core.bankmachine import *
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from litedram.core.multiplexer import *
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@ -30,7 +30,7 @@ class LiteDRAMController(Module):
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geom_settings.bankbits,
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phy_settings.dfi_databits,
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phy_settings.nphases)
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self.lasmic = bus.Interface(
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self.lasmic = common.Interface(
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aw=geom_settings.rowbits + geom_settings.colbits - address_align,
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dw=phy_settings.dfi_databits*phy_settings.nphases,
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nbanks=2**geom_settings.bankbits,
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@ -4,7 +4,7 @@ from operator import or_
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from litex.gen import *
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from litex.gen.genlib import roundrobin
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from litedram.bus import *
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from litedram.common import *
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class LiteDRAMCrossbar(Module):
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