phy/ecp5ddrphy: set cmd_delay from YAML config
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@ -566,7 +566,8 @@ class LiteDRAMCore(SoCCore):
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assert core_config["memtype"] in ["DDR3"]
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self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"](
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pads = platform.request("ddram"),
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq,
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cmd_delay = core_config["cmd_delay"])
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self.ddrphy.settings.add_electrical_settings(
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rtt_nom = core_config["rtt_nom"],
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rtt_wr = core_config["rtt_wr"],
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