common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter.

This commit is contained in:
Florent Kermarrec 2020-08-05 12:17:25 +02:00
parent 06f7192fb6
commit 9c5ce52b88
2 changed files with 11 additions and 8 deletions

View File

@ -273,14 +273,13 @@ class LiteDRAMNativePort(Settings):
def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0): def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0):
self.set_attributes(locals()) self.set_attributes(locals())
self.flush = Signal()
self.lock = Signal() self.lock = Signal()
self.cmd = stream.Endpoint(cmd_description(address_width)) self.cmd = stream.Endpoint(cmd_description(address_width))
self.wdata = stream.Endpoint(wdata_description(data_width)) self.wdata = stream.Endpoint(wdata_description(data_width))
self.rdata = stream.Endpoint(rdata_description(data_width)) self.rdata = stream.Endpoint(rdata_description(data_width))
self.flush = Signal()
# retro-compatibility # FIXME: remove # retro-compatibility # FIXME: remove
self.aw = self.address_width self.aw = self.address_width
self.dw = self.data_width self.dw = self.data_width
@ -300,6 +299,14 @@ class LiteDRAMNativePort(Settings):
else: else:
return self.cmd.addr[:cba_shift] return self.cmd.addr[:cba_shift]
def connect(self, port):
return [
self.cmd.connect(port.cmd),
self.wdata.connect(port.wdata),
port.rdata.connect(self.rdata),
port.flush.eq(self.flush),
self.lock.eq(port.lock),
]
class LiteDRAMNativeWritePort(LiteDRAMNativePort): class LiteDRAMNativeWritePort(LiteDRAMNativePort):
def __init__(self, *args, **kwargs): def __init__(self, *args, **kwargs):

View File

@ -358,8 +358,4 @@ class LiteDRAMNativePortConverter(Module):
self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse) self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse)
else: else:
# Identity # Identity
self.comb += [ self.comb += port_from.connect(port_to)
port_from.cmd.connect(port_to.cmd),
port_from.wdata.connect(port_to.wdata),
port_to.rdata.connect(port_from.rdata)
]