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litedram_gen: Add Auto-Flush to UART in FIFO mode. 

In FIFO mode, backpressure is propagated to the UART and would stall the CPU
when the UART is not accepting data. Enable Auto-Flush on the UART to allow
DRAM initialization when the UART is not ready.
This commit is contained in:
Florent Kermarrec 2021-09-24 13:37:19 +02:00
parent e52ece0b8a
commit 9e9c83ce40
1 changed files with 1 additions and 0 deletions
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litedram/gen.py
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@ -495,6 +495,7 @@ class LiteDRAMCore(SoCCore):
platform.add_extension(get_uart_fifo_ios()) platform.add_extension(get_uart_fifo_ios())
uart_interface = RS232PHYInterface() uart_interface = RS232PHYInterface()
self.submodules.uart = UART(uart_interface, tx_fifo_depth=1, rx_fifo_depth=1) self.submodules.uart = UART(uart_interface, tx_fifo_depth=1, rx_fifo_depth=1)
self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128)
uart_tx_pads = platform.request("uart_tx") uart_tx_pads = platform.request("uart_tx")
uart_rx_pads = platform.request("uart_rx") uart_rx_pads = platform.request("uart_rx")
self.comb += [ self.comb += [