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phy/lpddr5/sim: add DFITimingsChecker

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Jędrzej Boczar 2021-07-22 12:34:34 +02:00 committed by Alessandro Comodi
parent 91f14b2414
commit 9ef6e4b444
1 changed files with 15 additions and 16 deletions
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31
litedram/phy/lpddr5/simsoc.py
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@ -182,21 +182,21 @@ class SimSoC(SoCCore):
self.submodules.ddrctrl = LiteDRAMCoreControl() self.submodules.ddrctrl = LiteDRAMCoreControl()
self.sync += If(self.ddrctrl.init_done.storage, Finish()) self.sync += If(self.ddrctrl.init_done.storage, Finish())
# # Reuse DFITimingsChecker from phy/model.py # Reuse DFITimingsChecker from phy/model.py
# nphases = self.sdram.controller.settings.phy.nphases nphases = self.sdram.controller.settings.phy.nphases
# timings = {"tCK": (1e9 / sys_clk_freq) / nphases} timings = {"tCK": (1e9 / sys_clk_freq) / nphases}
# for name in _speedgrade_timings + _technology_timings: for name in _speedgrade_timings + _technology_timings:
# timings[name] = sdram_module.get(name) timings[name] = sdram_module.get(name)
#
# self.submodules.dfi_timings_checker = DFITimingsChecker( self.submodules.dfi_timings_checker = DFITimingsChecker(
# dfi = self.ddrphy.dfi, dfi = self.ddrphy.dfi,
# nbanks = 2**self.sdram.controller.settings.geom.bankbits, nbanks = 2**self.sdram.controller.settings.geom.bankbits,
# nphases = nphases, nphases = nphases,
# timings = timings, timings = timings,
# refresh_mode = sdram_module.timing_settings.fine_refresh_mode, refresh_mode = sdram_module.timing_settings.fine_refresh_mode,
# memtype = self.sdram.controller.settings.phy.memtype, memtype = self.sdram.controller.settings.phy.memtype,
# verbose = False, verbose = False,
# ) )
# Debug info ------------------------------------------------------------------------------- # Debug info -------------------------------------------------------------------------------
def dump(obj): def dump(obj):
@ -381,4 +381,3 @@ def main():
if __name__ == "__main__": if __name__ == "__main__":
main() main()