init: revert bitslips changed to 16 for phys other than S7LPDDR4PHY
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@ -698,7 +698,11 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
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r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
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r += "#define SDRAM_PHY_DELAYS 512\n"
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r += "#define SDRAM_PHY_BITSLIPS 8\n"
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elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY", "S7LPDDR4PHY"]:
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elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
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r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
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r += "#define SDRAM_PHY_DELAYS 32\n"
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r += "#define SDRAM_PHY_BITSLIPS 8\n"
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elif phytype in ["S7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
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r += "#define SDRAM_PHY_DELAYS 32\n"
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r += "#define SDRAM_PHY_BITSLIPS 16\n"
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