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litedram/init/get_sdram_phy_c_header: add CL/CWL defines.

This commit is contained in:
Florent Kermarrec 2020-09-30 19:19:31 +02:00
parent 6d063b196c
commit a611778e3d
1 changed files with 4 additions and 0 deletions
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4
litedram/init.py
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@ -485,6 +485,10 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
r += "#define SDRAM_PHY_XDR "+str(1 if phy_settings.memtype == "SDR" else 2) + "\n"
r += "#define SDRAM_PHY_DATABITS "+str(phy_settings.databits) + "\n"
r += "#define SDRAM_PHY_PHASES "+str(nphases)+"\n"
if phy_settings.cl is not None:
r += "#define SDRAM_PHY_CL "+str(phy_settings.cl)+"\n"
if phy_settings.cwl is not None:
r += "#define SDRAM_PHY_CWL "+str(phy_settings.cwl)+"\n"
if phy_settings.cmd_latency is not None:
r += "#define SDRAM_PHY_CMD_LATENCY "+str(phy_settings.cmd_latency)+"\n"
if phy_settings.cmd_delay is not None: