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init/get_sdram_phy_c_header: add support for dynamic write/read phases.

This commit is contained in:
Florent Kermarrec 2020-09-30 17:07:34 +02:00
parent c4d7083677
commit a67aed2a02
1 changed files with 12 additions and 17 deletions
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29
litedram/init.py
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@ -9,7 +9,7 @@
# Copyright (c) 2019 Gabriel L. Somlo <gsomlo@gmail.com> # Copyright (c) 2019 Gabriel L. Somlo <gsomlo@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from migen import log2_int from migen import *
cmds = { cmds = {
"PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS", "PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
@ -490,6 +490,14 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
if phy_settings.cmd_delay is not None: if phy_settings.cmd_delay is not None:
r += "#define SDRAM_PHY_CMD_DELAY "+str(phy_settings.cmd_delay)+"\n" r += "#define SDRAM_PHY_CMD_DELAY "+str(phy_settings.cmd_delay)+"\n"
# Define PHY Read.Write phases
rdphase = phy_settings.rdphase
if isinstance(rdphase, Signal): rdphase = rdphase.reset.value
r += "#define SDRAM_PHY_RDPHASE "+str(rdphase)+"\n"
wrphase = phy_settings.wrphase
if isinstance(wrphase, Signal): wrphase = wrphase.reset.value
r += "#define SDRAM_PHY_WRPHASE "+str(wrphase)+"\n"
# Define Read/Write Leveling capability # Define Read/Write Leveling capability
if phytype in ["USDDRPHY", "USPDDRPHY", "K7DDRPHY", "V7DDRPHY"]: if phytype in ["USDDRPHY", "USPDDRPHY", "K7DDRPHY", "V7DDRPHY"]:
r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n" r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n"
@ -520,7 +528,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
r += "static void cdelay(int i);\n" r += "static void cdelay(int i);\n"
# commands_px functions # Commands functions
for n in range(nphases): for n in range(nphases):
r += """ r += """
__attribute__((unused)) static void command_p{n}(int cmd) __attribute__((unused)) static void command_p{n}(int cmd)
@ -530,20 +538,7 @@ __attribute__((unused)) static void command_p{n}(int cmd)
}}""".format(n=str(n)) }}""".format(n=str(n))
r += "\n\n" r += "\n\n"
# rd/wr access macros # Write/Read functions
r += """
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
#define command_prd(X) command_p{rdphase}(X)
#define command_pwr(X) command_p{wrphase}(X)
""".format(rdphase=str(phy_settings.rdphase), wrphase=str(phy_settings.wrphase))
r += "\n"
#
# sdrrd/sdrwr functions utilities
#
r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n" r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
sdram_dfii_pix_wrdata_addr = [] sdram_dfii_pix_wrdata_addr = []
for n in range(nphases): for n in range(nphases):
@ -567,7 +562,7 @@ const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {{
init_sequence, mr1 = get_sdram_phy_init_sequence(phy_settings, timing_settings) init_sequence, mr1 = get_sdram_phy_init_sequence(phy_settings, timing_settings)
if phy_settings.memtype in ["DDR3", "DDR4"]: if phy_settings.memtype in ["DDR3", "DDR4"]:
# the value of MR1 needs to be modified during write leveling # The value of MR1 needs to be modified during write leveling
r += "#define DDRX_MR1 {}\n\n".format(mr1) r += "#define DDRX_MR1 {}\n\n".format(mr1)
r += "static void init_sequence(void)\n{\n" r += "static void init_sequence(void)\n{\n"