common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value
Fix SDRAM build with Yosys
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@ -165,11 +165,12 @@ def cmd_request_rw_layout(a, ba):
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class tXXDController(Module):
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def __init__(self, txxd):
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self.valid = valid = Signal()
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self.ready = ready = Signal(reset=1)
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self.ready = ready = Signal()
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ready.attr.add("no_retiming")
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# # #
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self.comb += self.ready.eq(1)
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if txxd is not None:
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count = Signal(max=max(txxd, 2))
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self.sync += \
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