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Merge pull request #154 from antmicro/ddr4-sodimm 

modules: add KVR21SE15S8/4 SO-DIMM
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enjoy-digital 2020-02-26 15:16:22 +01:00 committed by GitHub
parent 752e006cf9 3b0ec8f996
commit a753a3393d
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1 changed files with 18 additions and 0 deletions
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litedram/modules.py
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@ -557,3 +557,21 @@ class MT40A512M16(SDRAMModule):
"2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32), "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
} }
speedgrade_timings["default"] = speedgrade_timings["2400"] speedgrade_timings["default"] = speedgrade_timings["2400"]
# DDR4 (SO-DIMM) -----------------------------------------------------------------------------------
class KVR21SE15S84(SDRAMModule):
memtype = "DDR4"
# geometry
ngroupbanks = 4
ngroups = 4
nbanks = ngroups * ngroupbanks
nrows = 32768
ncols = 1024
# timings
trefi = {"1x": 64e6/8192, "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
trfc = {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
speedgrade_timings = {
"2133": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=33),
}
speedgrade_timings["default"] = speedgrade_timings["2133"]