Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

test: start fixing bist_tb

This commit is contained in:
Florent Kermarrec 2016-12-17 19:24:12 +01:00
parent 0f151c5499
commit aac61f346e
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
test/bist_tb.py
View File

@ -129,27 +129,27 @@ def main_generator(dut, mem):
yield from toggle_re(dut.checker.start) yield from toggle_re(dut.checker.start)
for i in range(8): for i in range(8):
yield yield
while((yield dut.checker.core.error) == 0): while((yield dut.checker.core.data_error) == 0):
yield yield
err_addr = yield dut.checker.core._data_counter + dut.checker.core.base err_addr = yield dut.checker.core.data_counter + dut.checker.core.base
assert err_addr == 20, err_addr assert err_addr == 20, err_addr
err_expect = yield dut.checker.core.expect err_expect = yield dut.checker.core.gen.o
assert err_expect == 0xffff000f, hex(err_expect) assert err_expect == 0xffff000f, hex(err_expect)
err_actual = yield dut.checker.core.actual err_actual = yield dut.checker.core.dma.source.data
assert err_actual == 0x200, err_actual assert err_actual == 0x200, err_actual
yield yield
errors = yield dut.checker.core.err_count errors = yield dut.checker.core.err_count
assert errors == 1, errors assert errors == 1, errors
while((yield dut.checker.core.error) == 0): while((yield dut.checker.core.data_error) == 0):
yield yield
err_addr = yield dut.checker.core._data_counter + dut.checker.core.base err_addr = yield dut.checker.core.data_counter + dut.checker.core.base
assert err_addr == 21, err_addr assert err_addr == 21, err_addr
err_expect = yield dut.checker.core.expect err_expect = yield dut.checker.core.gen.o
assert err_expect == 0xfff1ff1f, hex(err_expect) assert err_expect == 0xfff1ff1f, hex(err_expect)
err_actual = yield dut.checker.core.actual err_actual = yield dut.checker.core.dma.source.data
assert err_actual == 0x210, hex(err_actual) assert err_actual == 0x210, hex(err_actual)
yield yield
errors = yield dut.checker.core.err_count errors = yield dut.checker.core.err_count

4
test/common.py
View File

@ -14,8 +14,8 @@ def toggle_re(reg):
def reset_bist_module(module): def reset_bist_module(module):
# Toggle the reset # Toggle the reset
yield from toggle_re(module.reset) yield from toggle_re(module.reset)
# Takes 8 more clock cycles for the reset to have an effect # Takes a few clock cycles for the reset to have an effect
for i in range(8): for i in range(16):
yield yield
# Check some initial conditions are correct after reset. # Check some initial conditions are correct after reset.