test: start fixing bist_tb
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0f151c5499
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@ -129,27 +129,27 @@ def main_generator(dut, mem):
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yield from toggle_re(dut.checker.start)
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for i in range(8):
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yield
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while((yield dut.checker.core.error) == 0):
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while((yield dut.checker.core.data_error) == 0):
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yield
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err_addr = yield dut.checker.core._data_counter + dut.checker.core.base
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err_addr = yield dut.checker.core.data_counter + dut.checker.core.base
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assert err_addr == 20, err_addr
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err_expect = yield dut.checker.core.expect
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err_expect = yield dut.checker.core.gen.o
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assert err_expect == 0xffff000f, hex(err_expect)
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err_actual = yield dut.checker.core.actual
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err_actual = yield dut.checker.core.dma.source.data
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assert err_actual == 0x200, err_actual
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yield
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errors = yield dut.checker.core.err_count
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assert errors == 1, errors
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while((yield dut.checker.core.error) == 0):
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while((yield dut.checker.core.data_error) == 0):
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yield
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err_addr = yield dut.checker.core._data_counter + dut.checker.core.base
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err_addr = yield dut.checker.core.data_counter + dut.checker.core.base
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assert err_addr == 21, err_addr
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err_expect = yield dut.checker.core.expect
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err_expect = yield dut.checker.core.gen.o
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assert err_expect == 0xfff1ff1f, hex(err_expect)
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err_actual = yield dut.checker.core.actual
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err_actual = yield dut.checker.core.dma.source.data
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assert err_actual == 0x210, hex(err_actual)
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yield
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errors = yield dut.checker.core.err_count
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@ -14,8 +14,8 @@ def toggle_re(reg):
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def reset_bist_module(module):
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# Toggle the reset
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yield from toggle_re(module.reset)
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# Takes 8 more clock cycles for the reset to have an effect
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for i in range(8):
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# Takes a few clock cycles for the reset to have an effect
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for i in range(16):
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yield
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# Check some initial conditions are correct after reset.
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