core: change cba_shift parameter to more explicit address_mapping parameter
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230ea24113
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@ -71,6 +71,7 @@ def data_layout(data_width):
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class LiteDRAMInterface(Record):
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class LiteDRAMInterface(Record):
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def __init__(self, address_align, settings):
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def __init__(self, address_align, settings):
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rankbits = log2_int(settings.phy.nranks)
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rankbits = log2_int(settings.phy.nranks)
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self.address_align = address_align
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self.address_width = settings.geom.rowbits + settings.geom.colbits + rankbits - address_align
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self.address_width = settings.geom.rowbits + settings.geom.colbits + rankbits - address_align
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self.data_width = settings.phy.dfi_databits*settings.phy.nphases
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self.data_width = settings.phy.dfi_databits*settings.phy.nphases
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self.nbanks = settings.phy.nranks*(2**settings.geom.bankbits)
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self.nbanks = settings.phy.nranks*(2**settings.geom.bankbits)
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@ -22,6 +22,7 @@ class ControllerSettings(Settings):
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class LiteDRAMController(Module):
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class LiteDRAMController(Module):
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def __init__(self, phy_settings, geom_settings, timing_settings,
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def __init__(self, phy_settings, geom_settings, timing_settings,
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controller_settings=ControllerSettings()):
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controller_settings=ControllerSettings()):
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address_align = log2_int(burst_lengths[phy_settings.memtype])
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self.settings = settings = controller_settings
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self.settings = settings = controller_settings
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self.settings.phy = phy_settings
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self.settings.phy = phy_settings
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self.settings.geom = geom_settings
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self.settings.geom = geom_settings
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@ -34,13 +35,10 @@ class LiteDRAMController(Module):
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phy_settings.dfi_databits,
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phy_settings.dfi_databits,
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phy_settings.nphases)
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phy_settings.nphases)
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address_align = log2_int(burst_lengths[phy_settings.memtype])
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self.interface = interface = LiteDRAMInterface(address_align, settings)
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self.interface = interface = LiteDRAMInterface(address_align, settings)
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# # #
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# # #
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self.nrowbits = settings.geom.colbits - address_align # FIXME
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# refresher
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# refresher
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refresher = Refresher(settings)
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refresher = Refresher(settings)
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self.submodules += refresher
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self.submodules += refresher
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@ -12,10 +12,14 @@ from litedram.common import *
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from litedram.frontend.adaptation import *
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from litedram.frontend.adaptation import *
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ROW_BANK_COL = 0b01
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ROW_COL_BANK = 0b10
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class LiteDRAMCrossbar(Module):
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class LiteDRAMCrossbar(Module):
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def __init__(self, controller, cba_shift):
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def __init__(self, controller, address_mapping=ROW_BANK_COL):
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self.controller = controller
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self.controller = controller
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self.cba_shift = cba_shift
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self.address_mapping = address_mapping
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self.rca_bits = controller.address_width
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self.rca_bits = controller.address_width
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self.nbanks = controller.nbanks
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self.nbanks = controller.nbanks
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@ -86,8 +90,17 @@ class LiteDRAMCrossbar(Module):
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def do_finalize(self):
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def do_finalize(self):
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nmasters = len(self.masters)
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nmasters = len(self.masters)
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m_ba = [m.get_bank_address(self.bank_bits, self.cba_shift)for m in self.masters]
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# address mapping
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m_rca = [m.get_row_column_address(self.bank_bits, self.rca_bits, self.cba_shift) for m in self.masters]
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cba_shift = {
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ROW_BANK_COL: self.controller.settings.geom.colbits -
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self.controller.address_align,
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ROW_COL_BANK: self.controller.settings.geom.rowbits +
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self.controller.settings.geom.colbits -
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self.controller.address_align
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}
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m_ba = [m.get_bank_address(self.bank_bits, cba_shift[self.address_mapping])for m in self.masters]
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m_rca = [m.get_row_column_address(self.bank_bits, self.rca_bits, cba_shift[self.address_mapping]) for m in self.masters]
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controller = self.controller
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controller = self.controller
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master_readys = [0]*nmasters
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master_readys = [0]*nmasters
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