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phy/s7ddrphy: add dynamic read/write phase support.

This commit is contained in:
Florent Kermarrec 2020-09-30 17:13:41 +02:00
parent a67aed2a02
commit afe29d4231
1 changed files with 21 additions and 11 deletions
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32
litedram/phy/s7ddrphy.py
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@ -50,10 +50,12 @@ class S7DDRPHY(Module, AutoCSR):
} }
half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq])) half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency cwl = cwl + cmd_latency
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
# Registers -------------------------------------------------------------------------------- # Registers --------------------------------------------------------------------------------
self._rst = CSRStorage() self._rst = CSRStorage()
@ -81,9 +83,17 @@ class S7DDRPHY(Module, AutoCSR):
self._wdly_dqs_rst = CSR() self._wdly_dqs_rst = CSR()
self._wdly_dqs_inc = CSR() self._wdly_dqs_inc = CSR()
self._rdphase = CSRStorage(2, reset=rdphase)
self._wrphase = CSRStorage(2, reset=wrphase)
# PHY settings ----------------------------------------------------------------------------- # PHY settings -----------------------------------------------------------------------------
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl) _rdphase = self._rdphase.storage
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl) _wrphase = self._wrphase.storage
_rdcmdphase = Signal(2)
_wrcmdphase = Signal(2)
self.comb += _rdcmdphase.eq(_rdphase - 1)
self.comb += _wrcmdphase.eq(_wrphase - 1)
self.settings = PhySettings( self.settings = PhySettings(
phytype = phytype, phytype = phytype,
memtype = memtype, memtype = memtype,
@ -91,13 +101,13 @@ class S7DDRPHY(Module, AutoCSR):
dfi_databits = 2*databits, dfi_databits = 2*databits,
nranks = nranks, nranks = nranks,
nphases = nphases, nphases = nphases,
rdphase = rdphase, rdphase = _rdphase,
wrphase = wrphase, wrphase = _wrphase,
rdcmdphase = rdcmdphase, rdcmdphase = _rdcmdphase,
wrcmdphase = wrcmdphase, wrcmdphase = _wrcmdphase,
cl = cl, cl = cl,
cwl = cwl - cmd_latency, cwl = cwl - cmd_latency,
read_latency = 2 + cl_sys_latency + 2 + 2, read_latency = cl_sys_latency + 6,
write_latency = cwl_sys_latency, write_latency = cwl_sys_latency,
cmd_latency = cmd_latency, cmd_latency = cmd_latency,
cmd_delay = cmd_delay, cmd_delay = cmd_delay,