phy/s7ddrphy: add dynamic read/write phase support.

This commit is contained in:
Florent Kermarrec 2020-09-30 17:13:41 +02:00
parent a67aed2a02
commit afe29d4231
1 changed files with 21 additions and 11 deletions

View File

@ -54,6 +54,8 @@ class S7DDRPHY(Module, AutoCSR):
cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency
cwl_sys_latency = get_sys_latency(nphases, cwl)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
# Registers --------------------------------------------------------------------------------
self._rst = CSRStorage()
@ -81,9 +83,17 @@ class S7DDRPHY(Module, AutoCSR):
self._wdly_dqs_rst = CSR()
self._wdly_dqs_inc = CSR()
self._rdphase = CSRStorage(2, reset=rdphase)
self._wrphase = CSRStorage(2, reset=wrphase)
# PHY settings -----------------------------------------------------------------------------
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
_rdphase = self._rdphase.storage
_wrphase = self._wrphase.storage
_rdcmdphase = Signal(2)
_wrcmdphase = Signal(2)
self.comb += _rdcmdphase.eq(_rdphase - 1)
self.comb += _wrcmdphase.eq(_wrphase - 1)
self.settings = PhySettings(
phytype = phytype,
memtype = memtype,
@ -91,13 +101,13 @@ class S7DDRPHY(Module, AutoCSR):
dfi_databits = 2*databits,
nranks = nranks,
nphases = nphases,
rdphase = rdphase,
wrphase = wrphase,
rdcmdphase = rdcmdphase,
wrcmdphase = wrcmdphase,
rdphase = _rdphase,
wrphase = _wrphase,
rdcmdphase = _rdcmdphase,
wrcmdphase = _wrcmdphase,
cl = cl,
cwl = cwl - cmd_latency,
read_latency = 2 + cl_sys_latency + 2 + 2,
read_latency = cl_sys_latency + 6,
write_latency = cwl_sys_latency,
cmd_latency = cmd_latency,
cmd_delay = cmd_delay,