phy/s7ddrphy: add dynamic read/write phase support.
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@ -50,10 +50,12 @@ class S7DDRPHY(Module, AutoCSR):
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}
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half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
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cl, cwl = get_cl_cw(memtype, tck)
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cl_sys_latency = get_sys_latency(nphases, cl)
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cwl = cwl + cmd_latency
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cwl_sys_latency = get_sys_latency(nphases, cwl)
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cl, cwl = get_cl_cw(memtype, tck)
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cl_sys_latency = get_sys_latency(nphases, cl)
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cwl = cwl + cmd_latency
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cwl_sys_latency = get_sys_latency(nphases, cwl)
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rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
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wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
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# Registers --------------------------------------------------------------------------------
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self._rst = CSRStorage()
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@ -81,9 +83,17 @@ class S7DDRPHY(Module, AutoCSR):
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self._wdly_dqs_rst = CSR()
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self._wdly_dqs_inc = CSR()
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self._rdphase = CSRStorage(2, reset=rdphase)
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self._wrphase = CSRStorage(2, reset=wrphase)
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# PHY settings -----------------------------------------------------------------------------
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rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
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wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
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_rdphase = self._rdphase.storage
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_wrphase = self._wrphase.storage
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_rdcmdphase = Signal(2)
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_wrcmdphase = Signal(2)
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self.comb += _rdcmdphase.eq(_rdphase - 1)
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self.comb += _wrcmdphase.eq(_wrphase - 1)
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self.settings = PhySettings(
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phytype = phytype,
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memtype = memtype,
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@ -91,13 +101,13 @@ class S7DDRPHY(Module, AutoCSR):
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dfi_databits = 2*databits,
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nranks = nranks,
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nphases = nphases,
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rdphase = rdphase,
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wrphase = wrphase,
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rdcmdphase = rdcmdphase,
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wrcmdphase = wrcmdphase,
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rdphase = _rdphase,
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wrphase = _wrphase,
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rdcmdphase = _rdcmdphase,
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wrcmdphase = _wrcmdphase,
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cl = cl,
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cwl = cwl - cmd_latency,
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read_latency = 2 + cl_sys_latency + 2 + 2,
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read_latency = cl_sys_latency + 6,
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write_latency = cwl_sys_latency,
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cmd_latency = cmd_latency,
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cmd_delay = cmd_delay,
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