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frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ

This commit is contained in:
Jędrzej Boczar 2020-05-13 10:14:00 +02:00
parent 79314f9549
commit b0bde294c0
1 changed files with 6 additions and 6 deletions
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12
litedram/frontend/wishbone.py
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@ -28,16 +28,16 @@ class LiteDRAMWishbone2Native(Module):
[("data", port_data_width), ("we", port_data_width//8)], [("data", port_data_width), ("we", port_data_width//8)],
) )
self.submodules += wdata_converter self.submodules += wdata_converter
wdata_lock = Signal() wdata_complete = Signal()
self.comb += [ self.comb += [
wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we & ~wdata_lock), wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we & ~wdata_complete),
wdata_converter.sink.data.eq(wishbone.dat_w), wdata_converter.sink.data.eq(wishbone.dat_w),
wdata_converter.sink.we.eq(wishbone.sel), wdata_converter.sink.we.eq(wishbone.sel),
wdata_converter.source.connect(port.wdata) wdata_converter.source.connect(port.wdata)
] ]
self.sync += [ self.sync += [
If(wdata_converter.sink.valid & wdata_converter.sink.ready, If(wdata_converter.sink.valid & wdata_converter.sink.ready,
wdata_lock.eq(1) wdata_complete.eq(1)
) )
] ]
@ -75,9 +75,9 @@ class LiteDRAMWishbone2Native(Module):
) )
) )
fsm.act("WAIT-WRITE", fsm.act("WAIT-WRITE",
If(wdata_converter.sink.ready, If(wdata_complete,
NextValue(wdata_lock, 0), wishbone.ack.eq(1),
wishbone.ack.eq(1), NextValue(wdata_complete, 0),
NextState("CMD") NextState("CMD")
) )
) )