bench/genesys2: add litescope on ddrphy.dfi.

2020-10-08 16:21:02 +02:00 · 2020-10-08 16:21:02 +02:00 · b24943e691
parent e5f4f828ad
commit b24943e691
1 changed files with 9 additions and 0 deletions
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@ -97,6 +97,15 @@ class BenchSoC(SoCCore):
        self.add_csr("ethphy")
        self.add_etherbone(phy=self.ethphy)

+        # Analyzer ---------------------------------------------------------------------------------
+        from litescope import LiteScopeAnalyzer
+        analyzer_signals = [self.ddrphy.dfi]
+        self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
+            depth        = 512,
+            clock_domain = "sys",
+            csr_csv      = "analyzer.csv")
+        self.add_csr("analyzer")
+
        # Leds -------------------------------------------------------------------------------------
        from litex.soc.cores.led import LedChaser
        self.submodules.leds = LedChaser(