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core/bankmachine: update comments

This commit is contained in:
Florent Kermarrec 2018-08-14 15:13:33 +02:00
parent c1b1b07b3c
commit b2f1f29384
1 changed files with 1 additions and 2 deletions
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3
litedram/core/bankmachine.py
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@ -87,6 +87,7 @@ class BankMachine(Module):
cmd.is_write)) cmd.is_write))
# Control and command generation FSM # Control and command generation FSM
# Note: tRRD, tFAW, tCCD, tWTR timings are enforced by the multiplexer
self.submodules.fsm = fsm = FSM() self.submodules.fsm = fsm = FSM()
fsm.act("REGULAR", fsm.act("REGULAR",
If(self.refresh_req, If(self.refresh_req,
@ -95,8 +96,6 @@ class BankMachine(Module):
If(has_openrow, If(has_openrow,
If(hit, If(hit,
If(cas_allowed, If(cas_allowed,
# Note: write-to-read specification is enforced by
# multiplexer
cmd.valid.eq(1), cmd.valid.eq(1),
If(cmd_buffer.source.we, If(cmd_buffer.source.we,
req.wdata_ready.eq(cmd.ready), req.wdata_ready.eq(cmd.ready),