Fix UpConverter reversed write mask
Signed-off-by: Andrew Butt <andrewb1999@gmail.com>
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@ -309,10 +309,17 @@ class LiteDRAMNativePortUpConverter(Module):
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# Replicate `sel` bits to match the width of port_to.wdata.we.
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wdata_sel = Signal.like(port_to.wdata.we)
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wdata_sel_parts = [
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Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits)
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for i in range(ratio)
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]
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if reverse:
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wdata_sel_parts = [
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Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits)
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for i in reverse(range(ratio))
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]
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else:
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wdata_sel_parts = [
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Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits)
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for i in range(ratio)
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]
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self.sync += \
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If(cmd_buffer.source.valid & cmd_buffer.source.we & wdata_chunk[ratio - 1],
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wdata_sel.eq(Cat(wdata_sel_parts))
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