Merge pull request #321 from antmicro/msieron/sdram-hw-test

frontend/bist: replicate LFSR output to fill the DRAM port

litedram/frontend/bist.py

@@ -8,6 +8,7 @@
 """Built In Self Test (BIST) modules for testing LiteDRAM functionality."""
 
 from functools import reduce
+from math import ceil
 from operator import xor
 
 from migen import *
@@ -51,10 +52,8 @@ class LFSR(Module):
             curval.insert(0, nv)
             curval.pop()
 
-        self.sync += [
+        self.sync += state.eq(Cat(*curval[:n_state]))
-            state.eq(Cat(*curval[:n_state])),
+        self.comb += self.o.eq(Cat(*curval))
-            self.o.eq(Cat(*curval))
-        ]
 
 # Counter ------------------------------------------------------------------------------------------
 
@@ -211,7 +210,12 @@ class _LiteDRAMBISTGenerator(Module):
             raise NotImplementedError
 
         self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
-        self.comb += dma.sink.data.eq(data_gen.o)
+        self.comb += dma.sink.data.eq(
+            Replicate(
+                data_gen.o,
+                ceil(dram_port.data_width / len(data_gen.o)),
+            )[:dram_port.data_width],
+        )
 
 
 @ResetInserter()
@@ -511,7 +515,10 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
             If(dma.source.valid,
                 data_gen.ce.eq(1),
                 NextValue(data_counter, data_counter + 1),
-                If(dma.source.data != data_gen.o[:min(len(data_gen.o), dram_port.data_width)],
+                If(dma.source.data != Replicate(
+                                          data_gen.o,
+                                          ceil(dram_port.data_width / len(data_gen.o)),
+                                      )[:dram_port.data_width],
                     NextValue(self.errors, self.errors + 1)
                 ),
                 If(data_counter == (self.length[ashift:] - 1),

litedram/gen.py

@@ -856,7 +856,7 @@ def main():
     builder_arguments = builder_argdict(args)
     builder_arguments["compile_gateware"] = False
 
-    soc     = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000)
+    soc     = LiteDRAMCore(platform, core_config, integrated_rom_size=0xC000)
     builder = Builder(soc, **builder_arguments)
     builder.build(build_name=args.name, regular_comb=False)
 

test/common.py

@@ -354,6 +354,21 @@ class MemoryTestDataMixin:
         )
         expected = data["32bit_long_sequential"]["expected"]
         expected[16//4:(16 + 64)//4] = list(range(64//4))
+
+        lfsr_out_width = 31
+        # replicate LFSR output to fill the data_width
+        for test_case, config in data.items():
+            expected = config["expected"]
+
+            # extract data width from test case name
+            data_width = int(test_case.split("bit")[0])
+
+            for i, value in enumerate(expected):
+                for _ in range(data_width, lfsr_out_width - 1, -lfsr_out_width):
+                    value |= value << lfsr_out_width
+                    value &= (1 << data_width) - 1
+                expected[i] = value
+
         return data
 
     @property