litedram_gen: add missing ECP5DDRPHY constant
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@ -348,6 +348,7 @@ class LiteDRAMCore(SoCSDRAM):
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pads = platform.request("ddram"),
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pads = platform.request("ddram"),
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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self.comb += crg.stop.eq(self.ddrphy.init.stop)
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self.comb += crg.stop.eq(self.ddrphy.init.stop)
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self.add_constant("ECP5DDRPHY", None)
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
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if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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assert core_config["memtype"] in ["DDR2", "DDR3"]
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assert core_config["memtype"] in ["DDR2", "DDR3"]
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