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test/refefence: Update.

This commit is contained in:
Florent Kermarrec 2021-05-18 11:26:40 +02:00
parent 0877a81b4b
commit b8cd26fa52
4 changed files with 70 additions and 52 deletions
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8
litedram/init.py
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@ -745,10 +745,10 @@ __attribute__((unused)) static inline void command_p{n}(int cmd)
# Write/Read functions # Write/Read functions
pix_addr_fmt = """ pix_addr_fmt = """
static inline unsigned long {name}(int phase){{ static inline unsigned long {name}(int phase){{
\tswitch (phase) {{ switch (phase) {{
\t\t{cases} {cases}
\t\tdefault: return 0; default: return 0;
\t}} }}
}} }}
""" """
get_cases = lambda addrs: ["case {}: return {};".format(i, addr) for i, addr in enumerate(addrs)] get_cases = lambda addrs: ["case {}: return {};".format(i, addr) for i, addr in enumerate(addrs)]

40
test/reference/ddr3_init.h
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@ -34,22 +34,22 @@
static void cdelay(int i); static void cdelay(int i);
__attribute__((unused)) static void command_p0(int cmd) __attribute__((unused)) static inline void command_p0(int cmd)
{ {
sdram_dfii_pi0_command_write(cmd); sdram_dfii_pi0_command_write(cmd);
sdram_dfii_pi0_command_issue_write(1); sdram_dfii_pi0_command_issue_write(1);
} }
__attribute__((unused)) static void command_p1(int cmd) __attribute__((unused)) static inline void command_p1(int cmd)
{ {
sdram_dfii_pi1_command_write(cmd); sdram_dfii_pi1_command_write(cmd);
sdram_dfii_pi1_command_issue_write(1); sdram_dfii_pi1_command_issue_write(1);
} }
__attribute__((unused)) static void command_p2(int cmd) __attribute__((unused)) static inline void command_p2(int cmd)
{ {
sdram_dfii_pi2_command_write(cmd); sdram_dfii_pi2_command_write(cmd);
sdram_dfii_pi2_command_issue_write(1); sdram_dfii_pi2_command_issue_write(1);
} }
__attribute__((unused)) static void command_p3(int cmd) __attribute__((unused)) static inline void command_p3(int cmd)
{ {
sdram_dfii_pi3_command_write(cmd); sdram_dfii_pi3_command_write(cmd);
sdram_dfii_pi3_command_issue_write(1); sdram_dfii_pi3_command_issue_write(1);
@ -57,25 +57,31 @@ __attribute__((unused)) static void command_p3(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = { static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
CSR_SDRAM_DFII_PI0_WRDATA_ADDR, switch (phase) {
CSR_SDRAM_DFII_PI1_WRDATA_ADDR, case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
CSR_SDRAM_DFII_PI2_WRDATA_ADDR, case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
CSR_SDRAM_DFII_PI3_WRDATA_ADDR case 2: return CSR_SDRAM_DFII_PI2_WRDATA_ADDR;
}; case 3: return CSR_SDRAM_DFII_PI3_WRDATA_ADDR;
default: return 0;
}
}
const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = { static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
CSR_SDRAM_DFII_PI0_RDDATA_ADDR, switch (phase) {
CSR_SDRAM_DFII_PI1_RDDATA_ADDR, case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
CSR_SDRAM_DFII_PI2_RDDATA_ADDR, case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
CSR_SDRAM_DFII_PI3_RDDATA_ADDR case 2: return CSR_SDRAM_DFII_PI2_RDDATA_ADDR;
}; case 3: return CSR_SDRAM_DFII_PI3_RDDATA_ADDR;
default: return 0;
}
}
#define DDRX_MR_WRLVL_ADDRESS 1 #define DDRX_MR_WRLVL_ADDRESS 1
#define DDRX_MR_WRLVL_RESET 6 #define DDRX_MR_WRLVL_RESET 6
#define DDRX_MR_WRLVL_BIT 7 #define DDRX_MR_WRLVL_BIT 7
static void init_sequence(void) static inline void init_sequence(void)
{ {
/* Release reset */ /* Release reset */
sdram_dfii_pi0_address_write(0x0); sdram_dfii_pi0_address_write(0x0);

40
test/reference/ddr4_init.h
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@ -33,22 +33,22 @@
static void cdelay(int i); static void cdelay(int i);
__attribute__((unused)) static void command_p0(int cmd) __attribute__((unused)) static inline void command_p0(int cmd)
{ {
sdram_dfii_pi0_command_write(cmd); sdram_dfii_pi0_command_write(cmd);
sdram_dfii_pi0_command_issue_write(1); sdram_dfii_pi0_command_issue_write(1);
} }
__attribute__((unused)) static void command_p1(int cmd) __attribute__((unused)) static inline void command_p1(int cmd)
{ {
sdram_dfii_pi1_command_write(cmd); sdram_dfii_pi1_command_write(cmd);
sdram_dfii_pi1_command_issue_write(1); sdram_dfii_pi1_command_issue_write(1);
} }
__attribute__((unused)) static void command_p2(int cmd) __attribute__((unused)) static inline void command_p2(int cmd)
{ {
sdram_dfii_pi2_command_write(cmd); sdram_dfii_pi2_command_write(cmd);
sdram_dfii_pi2_command_issue_write(1); sdram_dfii_pi2_command_issue_write(1);
} }
__attribute__((unused)) static void command_p3(int cmd) __attribute__((unused)) static inline void command_p3(int cmd)
{ {
sdram_dfii_pi3_command_write(cmd); sdram_dfii_pi3_command_write(cmd);
sdram_dfii_pi3_command_issue_write(1); sdram_dfii_pi3_command_issue_write(1);
@ -56,25 +56,31 @@ __attribute__((unused)) static void command_p3(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = { static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
CSR_SDRAM_DFII_PI0_WRDATA_ADDR, switch (phase) {
CSR_SDRAM_DFII_PI1_WRDATA_ADDR, case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
CSR_SDRAM_DFII_PI2_WRDATA_ADDR, case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
CSR_SDRAM_DFII_PI3_WRDATA_ADDR case 2: return CSR_SDRAM_DFII_PI2_WRDATA_ADDR;
}; case 3: return CSR_SDRAM_DFII_PI3_WRDATA_ADDR;
default: return 0;
}
}
const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = { static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
CSR_SDRAM_DFII_PI0_RDDATA_ADDR, switch (phase) {
CSR_SDRAM_DFII_PI1_RDDATA_ADDR, case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
CSR_SDRAM_DFII_PI2_RDDATA_ADDR, case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
CSR_SDRAM_DFII_PI3_RDDATA_ADDR case 2: return CSR_SDRAM_DFII_PI2_RDDATA_ADDR;
}; case 3: return CSR_SDRAM_DFII_PI3_RDDATA_ADDR;
default: return 0;
}
}
#define DDRX_MR_WRLVL_ADDRESS 1 #define DDRX_MR_WRLVL_ADDRESS 1
#define DDRX_MR_WRLVL_RESET 769 #define DDRX_MR_WRLVL_RESET 769
#define DDRX_MR_WRLVL_BIT 7 #define DDRX_MR_WRLVL_BIT 7
static void init_sequence(void) static inline void init_sequence(void)
{ {
/* Release reset */ /* Release reset */
sdram_dfii_pi0_address_write(0x0); sdram_dfii_pi0_address_write(0x0);

22
test/reference/sdr_init.h
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@ -27,7 +27,7 @@
static void cdelay(int i); static void cdelay(int i);
__attribute__((unused)) static void command_p0(int cmd) __attribute__((unused)) static inline void command_p0(int cmd)
{ {
sdram_dfii_pi0_command_write(cmd); sdram_dfii_pi0_command_write(cmd);
sdram_dfii_pi0_command_issue_write(1); sdram_dfii_pi0_command_issue_write(1);
@ -35,15 +35,21 @@ __attribute__((unused)) static void command_p0(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = { static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
CSR_SDRAM_DFII_PI0_WRDATA_ADDR switch (phase) {
}; case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
default: return 0;
}
}
const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = { static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
CSR_SDRAM_DFII_PI0_RDDATA_ADDR switch (phase) {
}; case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
default: return 0;
}
}
static void init_sequence(void) static inline void init_sequence(void)
{ {
/* Bring CKE high */ /* Bring CKE high */
sdram_dfii_pi0_address_write(0x0); sdram_dfii_pi0_address_write(0x0);