Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litedram_gen: set min_l2_data_width to 0 (l2_data_width will use controller's data_width)

This commit is contained in:
Florent Kermarrec 2020-01-20 19:15:43 +01:00
parent cee3a43685
commit ba9134a9a8
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litedram/gen.py
View File

@ -274,14 +274,14 @@ class LiteDRAMCore(SoCSDRAM):
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0 kwargs["integrated_sram_size"] = 0
kwargs["l2_size"] = 0 kwargs["l2_size"] = 0
kwargs["l2_data_width"] = 32 kwargs["min_l2_data_width"] = 0
kwargs["with_uart"] = False kwargs["with_uart"] = False
kwargs["with_timer"] = False kwargs["with_timer"] = False
kwargs["with_ctrl"] = False kwargs["with_ctrl"] = False
kwargs["with_wishbone"] = (cpu_type != None) kwargs["with_wishbone"] = (cpu_type != None)
else: else:
kwargs["l2_size"] = 0 kwargs["l2_size"] = 0
kwargs["l2_data_width"] = 32 kwargs["min_l2_data_width"] = 0
# SoCSDRAM --------------------------------------------------------------------------------- # SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq, SoCSDRAM.__init__(self, platform, sys_clk_freq,