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README: update

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Florent Kermarrec 2018-08-29 16:34:53 +02:00
parent 6f7ae8496b
commit bc8a9cef7d
1 changed files with 3 additions and 2 deletions
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@ -37,10 +37,11 @@ PHY:
Core: Core:
- Fully pipelined, high performance. - Fully pipelined, high performance.
- Configurable commands depth on bankmachines. - Configurable commands depth on bankmachines.
- Auto-Precharge.
Frontend: Frontend:
- Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!) - Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!)
- Ports arbitration transparent to the user. - Ports arbitration transparent to the user.
- Wishbone bridge. - Native, AXI-MM or Wishbone user interface.
- DMA reader/writer. - DMA reader/writer.
- BIST. - BIST.
@ -52,7 +53,7 @@ LiteDRAM is already used in commercial and open-source designs:
[> Possible improvements [> Possible improvements
------------------------ ------------------------
- add standardized interfaces (AXI, Avalon-ST) - add Avalon-ST interface.
- add support for Altera PHYs. - add support for Altera PHYs.
- add support for Lattice PHYs. - add support for Lattice PHYs.
- add more documentation - add more documentation