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frontend/dma: add fifo_buffered parameter

This commit is contained in:
Florent Kermarrec 2016-10-28 09:48:25 +02:00
parent 6e3f5e4d98
commit bd40268961
1 changed files with 4 additions and 4 deletions
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8
litedram/frontend/dma.py
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@ -4,7 +4,7 @@ from litex.soc.interconnect import stream
class LiteDRAMDMAReader(Module): class LiteDRAMDMAReader(Module):
def __init__(self, port, fifo_depth=16): def __init__(self, port, fifo_depth=16, fifo_buffered=False):
self.sink = sink = stream.Endpoint([("address", port.aw)]) self.sink = sink = stream.Endpoint([("address", port.aw)])
self.source = source = stream.Endpoint([("data", port.dw)]) self.source = source = stream.Endpoint([("data", port.dw)])
@ -37,7 +37,7 @@ class LiteDRAMDMAReader(Module):
self.comb += request_enable.eq(rsv_level != fifo_depth) self.comb += request_enable.eq(rsv_level != fifo_depth)
# FIFO # FIFO
fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth) fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth, fifo_buffered)
self.submodules += fifo self.submodules += fifo
self.comb += [ self.comb += [
@ -48,13 +48,13 @@ class LiteDRAMDMAReader(Module):
class LiteDRAMDMAWriter(Module): class LiteDRAMDMAWriter(Module):
def __init__(self, port, fifo_depth=16): def __init__(self, port, fifo_depth=16, fifo_buffered=False):
self.sink = sink = stream.Endpoint([("address", port.aw), self.sink = sink = stream.Endpoint([("address", port.aw),
("data", port.dw)]) ("data", port.dw)])
# # # # # #
fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth) fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth, fifo_buffered)
self.submodules += fifo self.submodules += fifo
self.comb += [ self.comb += [