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test/test_axi: split reads/writes generators

This commit is contained in:
Florent Kermarrec 2018-08-28 13:43:58 +02:00
parent 95cb7cdba5
commit c15c47497a
1 changed files with 26 additions and 14 deletions
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36
test/test_axi.py
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@ -25,9 +25,7 @@ class TestAXI(unittest.TestCase):
class Read(Access): class Read(Access):
pass pass
def writes_generator(axi_port, writes): def writes_cmd_data_generator(axi_port, writes):
self.writes_id_errors = 0
yield axi_port.b.ready.eq(1) # always accepting write response
for write in writes: for write in writes:
# send command # send command
yield axi_port.aw.valid.eq(1) yield axi_port.aw.valid.eq(1)
@ -45,6 +43,11 @@ class TestAXI(unittest.TestCase):
while (yield axi_port.w.ready) == 0: while (yield axi_port.w.ready) == 0:
yield yield
yield axi_port.w.valid.eq(0) yield axi_port.w.valid.eq(0)
def writes_response_generator(axi_port, writes):
self.writes_id_errors = 0
yield axi_port.b.ready.eq(1) # always accepting write response
for write in writes:
# wait response # wait response
while (yield axi_port.b.valid) == 0: while (yield axi_port.b.valid) == 0:
yield yield
@ -52,10 +55,7 @@ class TestAXI(unittest.TestCase):
self.writes_id_errors += 1 self.writes_id_errors += 1
yield yield
def reads_generator(axi_port, reads): def reads_cmd_generator(axi_port, reads):
self.reads_data_errors = 0
self.reads_id_errors = 0
yield axi_port.r.ready.eq(1) # always accepting read response
for read in reads: for read in reads:
# send command # send command
yield axi_port.ar.valid.eq(1) yield axi_port.ar.valid.eq(1)
@ -66,6 +66,12 @@ class TestAXI(unittest.TestCase):
yield yield
yield axi_port.ar.valid.eq(0) yield axi_port.ar.valid.eq(0)
yield yield
def reads_response_data_generator(axi_port, reads):
self.reads_data_errors = 0
self.reads_id_errors = 0
yield axi_port.r.ready.eq(1) # always accepting read response
for read in reads:
# wait data / response # wait data / response
while (yield axi_port.r.valid) == 0: while (yield axi_port.r.valid) == 0:
yield yield
@ -85,24 +91,30 @@ class TestAXI(unittest.TestCase):
prng = random.Random(42) prng = random.Random(42)
writes = [] writes = []
for i in range(64): for i in range(64):
# incrementing addr, random data &id
writes.append(Write(i, prng.randrange(2**32), prng.randrange(2**8))) writes.append(Write(i, prng.randrange(2**32), prng.randrange(2**8)))
# incrementing addr, data & id (debug)
#writes.append(Write(i, i, i))
reads = [] reads = []
for i in range(64): # dummy reads while content not yet written for i in range(64): # dummy reads while content not yet written
reads.append(Read(64, 0x00000000, 0x00)) reads.append(Read(64, 0x00000000, 0x00))
for i in range(64): for i in range(64):
# incrementing addr, written data, random id
reads.append(Read(i, writes[i].data, prng.randrange(2**8))) reads.append(Read(i, writes[i].data, prng.randrange(2**8)))
# incrementing addr, written data, incrementing id (debug)
#reads.append(Read(i, writes[i].data, i))
# simulation # simulation
generators = [ generators = [
writes_generator(axi_port, writes), writes_cmd_data_generator(axi_port, writes),
reads_generator(axi_port, reads), writes_response_generator(axi_port, writes),
reads_cmd_generator(axi_port, reads),
reads_response_data_generator(axi_port, reads),
mem.read_handler(dram_port), mem.read_handler(dram_port),
mem.write_handler(dram_port) mem.write_handler(dram_port)
] ]
run_simulation(dut, generators, vcd_name="axi2native.vcd") run_simulation(dut, generators, vcd_name="axi2native.vcd")
#mem.show_content()
mem.show_content()
self.assertEqual(self.writes_id_errors, 0) self.assertEqual(self.writes_id_errors, 0)
self.assertEqual(self.reads_data_errors, 0) self.assertEqual(self.reads_data_errors, 0)
self.assertEqual(self.reads_id_errors, 0) self.assertEqual(self.reads_id_errors, 0)