common/BitSlip: allow passing i/o signals as parameters.
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@ -117,9 +117,9 @@ class PHYPadsCombiner:
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# BitSlip ------------------------------------------------------------------------------------------
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# BitSlip ------------------------------------------------------------------------------------------
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class BitSlip(Module):
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class BitSlip(Module):
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def __init__(self, dw, rst=None, slp=None, cycles=1):
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def __init__(self, dw, i=None, o=None, rst=None, slp=None, cycles=1):
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self.i = Signal(dw)
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self.i = Signal(dw) if i is None else i
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self.o = Signal(dw)
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self.o = Signal(dw) if o is None else o
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self.rst = Signal() if rst is None else rst
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self.rst = Signal() if rst is None else rst
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self.slp = Signal() if slp is None else slp
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self.slp = Signal() if slp is None else slp
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