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Merge pull request #132 from antmicro/modules-fix-syntax-error 

modules: MT18KSF1G72HZ: use float as tWR value
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enjoy-digital 2020-02-06 09:43:43 +01:00 committed by GitHub
parent 4a3ad56146 6595567fa8
commit c2051df1c3
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litedram/modules.py
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@ -467,7 +467,7 @@ class MT18KSF1G72HZ(SDRAMModule):
speedgrade_timings = {
"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=None),
"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=None),
"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=(13.125, None), tRFC=(128, None), tFAW=(None, 40), tRAS=None),
"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=(128, None), tFAW=(None, 40), tRAS=None),
}
speedgrade_timings["default"] = speedgrade_timings["1600"]