init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS.
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@ -448,7 +448,20 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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def get_sdram_phy_c_header(phy_settings, timing_settings):
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def get_sdram_phy_c_header(phy_settings, timing_settings):
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r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
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r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
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r += "#include <hw/common.h>\n"
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r += "#include <generated/csr.h>\n"
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r += "#define DFII_CONTROL_SEL 0x01\n"
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r += "#define DFII_CONTROL_CKE 0x02\n"
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r += "#define DFII_CONTROL_ODT 0x04\n"
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r += "#define DFII_CONTROL_RESET_N 0x08\n"
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r += "#define DFII_COMMAND_CS 0x01\n"
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r += "#define DFII_COMMAND_WE 0x02\n"
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r += "#define DFII_COMMAND_CAS 0x04\n"
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r += "#define DFII_COMMAND_RAS 0x08\n"
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r += "#define DFII_COMMAND_WRDATA 0x10\n"
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r += "#define DFII_COMMAND_RDDATA 0x20\n"
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phytype = phy_settings.phytype.upper()
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phytype = phy_settings.phytype.upper()
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nphases = phy_settings.nphases
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nphases = phy_settings.nphases
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