frontend/avalon: Decouple Cmd and Data-paths in BURST-WRITE (We don't need to wait that wdata_fifo is empty to return to Idle).
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@ -104,9 +104,9 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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).Else(
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port.cmd.addr.eq(avalon.address - address_offset),
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port.cmd.we.eq(avalon.write),
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port.cmd.valid.eq(1),
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port.cmd.valid.eq(avalon.read | (avalon.write & wdata_fifo.sink.ready)),
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port.cmd.last.eq(1),
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If(port.cmd.ready,
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If(port.cmd.valid & port.cmd.ready,
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avalon.waitrequest.eq(0),
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If(port.cmd.we,
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NextState("SINGLE-WRITE")
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@ -137,21 +137,16 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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port.cmd.addr.eq(address),
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port.cmd.we.eq(1),
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port.cmd.valid.eq(avalon.write & wdata_fifo.sink.ready),
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port.cmd.last.eq(burst_count == 1),
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If(port.cmd.valid & port.cmd.ready,
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avalon.waitrequest.eq(0)
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),
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If(burst_count > 0,
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If(port.cmd.valid & port.cmd.ready,
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avalon.waitrequest.eq(0),
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If(port.cmd.last,
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NextState("IDLE")
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).Else(
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NextValue(burst_count, burst_count - 1),
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NextValue(address, address + burst_increment)
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)
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).Else(
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avalon.waitrequest.eq(1),
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# Wait for the FIFO to be empty
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If((~port.cmd.valid) & (~wdata_fifo.source.valid),
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NextState("IDLE")
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)
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),
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)
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)
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fsm.act("BURST-READ",
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