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phy/s7ddrphy: reduce BitSlip's cycles to 1 (seems to be enough for all cases).

This commit is contained in:
Florent Kermarrec 2020-09-15 19:50:45 +02:00
parent 26e45d1ce4
commit c3b4b0d338
2 changed files with 2 additions and 2 deletions
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2
litedram/init.py
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@ -506,7 +506,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
r += "#define SDRAM_PHY_DELAYS 32\n"
r += "#define SDRAM_PHY_BITSLIPS 16\n"
r += "#define SDRAM_PHY_BITSLIPS 8\n"
elif phytype in ["ECP5DDRPHY"]:
r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/4\n"
r += "#define SDRAM_PHY_DELAYS 8\n"

2
litedram/phy/s7ddrphy.py
View File

@ -511,7 +511,7 @@ class S7DDRPHY(Module, AutoCSR):
dq_bitslip = BitSlip(8,
rst = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip_rst.re,
slp = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip.re,
cycles = 2)
cycles = 1)
self.submodules += dq_bitslip
self.comb += dq_bitslip.i.eq(dq_i_data)
self.comb += [