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W9825G6KH6 seems to use 8192 refresh cycles not 8000

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Hans Baier 2021-11-06 07:33:31 +07:00
parent 3d1d711a43
commit c3ec0ab079
1 changed files with 1 additions and 1 deletions
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litedram/modules.py
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@ -541,7 +541,7 @@ class W9825G6KH6(SDRModule):
nrows = 8192 nrows = 8192
ncols = 512 ncols = 512
# timings # timings
technology_timings = _TechnologyTimings(tREFI=64e6/8000, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10)) technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 60), tFAW=None, tRAS=42)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 60), tFAW=None, tRAS=42)}
# DDR ---------------------------------------------------------------------------------------------- # DDR ----------------------------------------------------------------------------------------------