modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns)
This commit is contained in:
Florent Kermarrec
parent
370b05ecf1
commit
c4dad2402c
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@ -4,31 +4,47 @@ from migen import *
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from litedram.common import GeomSettings, TimingSettings
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# TODO:
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# - add speedgrade support
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# - specify tWTR, tFAW in ck or ns
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class SDRAMModule:
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def __init__(self, clk_freq, rate):
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"""SDRAM module geometry and timings.
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SDRAM controller has to ensure that all geometry and
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timings parameters are fulfilled. Timings parameters
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can be expressed in ns, in SDRAM clock cycles or both
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and controller needs to use the greater value.
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SDRAM modules with the same geometry exist can have
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various speedgrades.
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"""
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def __init__(self, clk_freq, rate, speedgrade=None):
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self.clk_freq = clk_freq
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self.rate = rate
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self.speedgrade = speedgrade
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self.geom_settings = GeomSettings(
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bankbits=log2_int(self.nbanks),
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rowbits=log2_int(self.nrows),
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colbits=log2_int(self.ncols),
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)
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self.timing_settings = TimingSettings(
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tRP=self.ns(self.tRP),
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tRCD=self.ns(self.tRCD),
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tWR=self.ns(self.tWR),
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tREFI=self.ns(self.tREFI, False),
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tRFC=self.ns(self.tRFC),
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tWTR=self.tWTR,
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tFAW=None if not hasattr(self, "tFAW") else self.tFAW
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tRP=self.ns_to_cycles(self.get("tRP")),
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tRCD=self.ns_to_cycles(self.get("tRCD")),
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tWR=self.ns_to_cycles(self.get("tWR")),
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tREFI=self.ns_to_cycles(self.get("tREFI"), False),
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tRFC=self.ns_to_cycles(self.get("tRFC")),
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tWTR=self.ck_ns_to_cycles(*self.get("tWTR")),
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tFAW=None if self.get("tFAW") is None else self.ck_ns_to_cycles(*self.get("tFAW"))
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)
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def ns(self, t, margin=True):
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clk_period_ns = 1000000000/self.clk_freq
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def get(self, name):
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if self.speedgrade is not None and name in ["tRP", "tRCD", "tWR", "tRFC", "tFAW"]:
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name += "_" + self.speedgrade
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try:
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return getattr(self, name)
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except:
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return None
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def ns_to_cycles(self, t, margin=True):
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clk_period_ns = 1e9/self.clk_freq
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if margin:
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margins = {
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"1:1" : 0,
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@ -38,6 +54,19 @@ class SDRAMModule:
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t += margins[self.rate]
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return ceil(t/clk_period_ns)
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def ck_to_cycles(self, c):
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d = {
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"1:1" : 1,
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"1:2" : 2,
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"1:4" : 4
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}
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return ceil(c/d[self.rate])
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def ck_ns_to_cycles(self, c, t):
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c = 0 if c is None else c
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t = 0 if t is None else t
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return max(self.ck_to_cycles(c), self.ns_to_cycles(t))
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# SDR
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class IS42S16160(SDRAMModule):
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@ -46,15 +75,14 @@ class IS42S16160(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 512
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# timings (ns)
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# speedgrade invariant timings
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tRP = 20
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tRCD = 20
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tWR = 20
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tREFI = 64*1000*1000/8192
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tREFI = 64e6/8192
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tRFC = 70
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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# speedgrade related timings
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tWTR = (2, None)
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class MT48LC4M16(SDRAMModule):
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@ -63,15 +91,14 @@ class MT48LC4M16(SDRAMModule):
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nbanks = 4
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nrows = 4096
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ncols = 256
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/4096
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tWTR = (2, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 14
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tREFI = 64*1000*1000/4096
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tRFC = 66
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class AS4C16M16(SDRAMModule):
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@ -80,16 +107,14 @@ class AS4C16M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 512
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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# speedgrade related timings
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tRP = 18
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tRCD = 18
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tWR = 12
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tREFI = 64*1000*1000/8192
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tRFC = 60
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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# DDR
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@ -99,15 +124,14 @@ class MT46V32M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 64*1000*1000/8192
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tRFC = 70
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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# LPDDR
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@ -117,15 +141,15 @@ class MT46H32M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 64*1000*1000/8192
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tRFC = 72
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class MT46H32M32(SDRAMModule):
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memtype = "LPDDR"
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@ -133,15 +157,14 @@ class MT46H32M32(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 64*1000*1000/8192
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tRFC = 72
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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# DDR2
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@ -151,15 +174,14 @@ class MT47H128M8(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (None, 7.5)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 7800
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tRFC = 127.5
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class MT47H64M16(SDRAMModule):
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@ -168,15 +190,15 @@ class MT47H64M16(SDRAMModule):
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nbanks = 8
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nrows = 8192
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ncols = 1024
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (None, 7.5)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 7800
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tREFI = 64e6/8192
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tRFC = 127.5
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = None
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class P3R1GE4JGF(SDRAMModule):
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@ -185,114 +207,131 @@ class P3R1GE4JGF(SDRAMModule):
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nbanks = 8
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nrows = 8192
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ncols = 1024
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# timings (ns)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (None, 7.5)
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# speedgrade related timings
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tRP = 12.5
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tRCD = 12.5
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tWR = 15
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tREFI = 7800
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tREFI = 64e6/8192
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tRFC = 127.5
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = None
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# DDR3
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class MT8JTF12864(SDRAMModule):
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 7800
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tRFC = 70
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# timings (sys_clk cycles)
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tWTR = 2
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tFAW = ceil(32/4)
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class MT41J128M16(SDRAMModule):
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings (ns)
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 64*1000*1000/16384
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (4, 7.5)
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# speedgrade related timings
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# DDR3-1066
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tRP_1066 = 13.1
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tRCD_1066 = 13.1
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tWR_1066 = 13.1
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tRFC_1066 = 86
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tFAW_1066 = (27, None)
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# DDR3-1333
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tRP_1333 = 13.5
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tRCD_1333 = 13.5
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tWR_1333 = 13.5
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tRFC_1333 = 107
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tFAW_1333 = (30, None)
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# DDR3-1600
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tRP_1600 = 13.75
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tRCD_1600 = 13.75
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tWR_1600 = 13.75
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tRFC_1600 = 128
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tFAW_1600 = (32, None)
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# API retro-compatibility
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tRP = tRP_1600
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tRCD = tRCD_1600
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tWR = tWR_1600
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tRFC = tRFC_1600
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tFAW = tFAW_1600
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class MT41K128M16(SDRAMModule):
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class MT41K128M16(MT41J128M16):
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pass
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class MT41J256M16(MT41J128M16):
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# geometry
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nrows = 32768
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# speedgrade related timings
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tRFC_1066 = 139
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tRFC_1333 = 174
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tRFC_1600 = 208
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class MT41K256M16(MT41J256M16):
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pass
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class MT8JTF12864(SDRAMModule):
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tREFI = 64*1000*1000/8192
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tRFC = 160
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (4, 7.5)
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# speedgrade related timings
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# DDR3-1066
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tRP_1066 = 15
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tRCD_1066 = 15
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tWR_1066 = 15
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tRFC_1066 = 86
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tFAW_1066 = (27, None)
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# DDR3-1333
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tRP_1333 = 15
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tRCD_1333 = 15
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tWR_1333 = 15
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tRFC_1333 = 107
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tFAW_1333 = (30, None)
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# API retro-compatibility
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tRP = tRP_1333
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tRCD = tRCD_1333
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tWR = tWR_1333
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tRFC = tRFC_1333
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tFAW = tFAW_1333
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class MT41K256M16(SDRAMModule):
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 32768
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ncols = 1024
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tREFI = 64*1000*1000/8192
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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class MT41J256M16(SDRAMModule):
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 32768
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ncols = 1024
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tREFI = 64*1000*1000/8192
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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class MT18KSF1G72HZ_1G6(SDRAMModule):
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class MT18KSF1G72HZ(SDRAMModule):
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 65536
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ncols = 1024
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# timings (ns)
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tRP = 13.75
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tRCD = 13.75
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tWR = 15
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tREFI = 64*1000*1000/8192
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tRFC = 260
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# timings (sys_clk cycles)
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tWTR = 3
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tFAW = ceil(32/4)
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (4, 7.5)
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# DDR3-1066
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tRP_1066 = 15
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tRCD_1066 = 15
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tWR_1066 = 15
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tRFC_1066 = 86
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tFAW_1066 = (27, None)
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# DDR3-1333
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tRP_1333 = 15
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tRCD_1333 = 15
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tWR_1333 = 15
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tRFC_1333 = 107
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tFAW_1333 = (30, None)
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# DDR3-1600
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tRP_1600 = 13.125
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tRCD_1600 = 13.125
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tWR_1600 = 13.125
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tRFC_1600 = 128
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tFAW_1600 = (32, None)
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# API retro-compatibility
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tRP = tRP_1600
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tRCD = tRCD_1600
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tWR = tWR_1600
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tRFC = tRFC_1600
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tFAW = tFAW_1600
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