bench: cleanup clocking on Ultrascale targets.

bench/kcu105.py

@@ -32,7 +32,7 @@ class _CRG(Module, AutoCSR):
         self.clock_domains.cd_sys     = ClockDomain()
         self.clock_domains.cd_sys4x   = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x   = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200  = ClockDomain()
+        self.clock_domains.cd_idelay  = ClockDomain()
         self.clock_domains.cd_uart    = ClockDomain()
         self.clock_domains.cd_eth     = ClockDomain()
 
@@ -42,7 +42,7 @@ class _CRG(Module, AutoCSR):
         self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
         main_pll.register_clkin(platform.request("clk125"), 125e6)
         main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
-        main_pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
+        main_pll.create_clkout(self.cd_idelay, 200e6, with_reset=False)
         main_pll.create_clkout(self.cd_uart,   100e6)
         main_pll.create_clkout(self.cd_eth,    200e6)
         main_pll.expose_drp()
@@ -53,15 +53,21 @@ class _CRG(Module, AutoCSR):
         pll.create_clkout(self.cd_pll4x,  sys_clk_freq*4, buf=None, with_reset=False)
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
-                p_BUFGCE_DIVIDE=4,
+                p_BUFGCE_DIVIDE = 4,
-                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
+                i_CE = 1,
-            Instance("BUFGCE", name="main_bufgce",
+                i_I  = self.cd_pll4x.clk,
-                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
+                o_O  = self.cd_sys.clk,
-            AsyncResetSynchronizer(self.cd_clk200, ~pll.locked),
+            ),
+            Instance("BUFGCE",
+                i_CE = 1,
+                i_I  = self.cd_pll4x.clk,
+                o_O  = self.cd_sys4x.clk,
+            ),
+            AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
         ]
 
-        self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys)
+        self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
 
         sys_clk_counter = Signal(32)
         self.sync += sys_clk_counter.eq(sys_clk_counter + 1)

bench/xcu1525.py

@@ -49,11 +49,17 @@ class _CRG(Module, AutoCSR):
         pll.create_clkout(self.cd_pll4x,  sys_clk_freq*4, buf=None, with_reset=False)
 
         self.specials += [
-            Instance("BUFGCE_DIV", name="main_bufgce_div",
+            Instance("BUFGCE_DIV",
-                p_BUFGCE_DIVIDE=4,
+                p_BUFGCE_DIVIDE = 4,
-                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
+                i_CE = 1,
-            Instance("BUFGCE", name="main_bufgce",
+                i_I  = self.cd_pll4x.clk,
-                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
+                o_O  = self.cd_sys.clk,
+            ),
+            Instance("BUFGCE",
+                i_CE = 1,
+                i_I  = self.cd_pll4x.clk,
+                o_O  = self.cd_sys4x.clk,
+            ),
             AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
         ]
 
@@ -94,7 +100,7 @@ class BenchSoC(SoCCore):
             size      = 0x40000000,
             with_bist = with_bist,
         )
-        # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
+        # Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
         platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")
 
         # UARTBone ---------------------------------------------------------------------------------