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core/controller: add simulation workaround for 1:2 ddr3 phy

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This commit is contained in:
Florent Kermarrec 2018-07-13 17:32:24 +02:00
parent bd09471a03
commit c9f2e30dcc
1 changed files with 3 additions and 0 deletions
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3
litedram/core/controller.py
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@ -54,6 +54,9 @@ class LiteDRAMController(Module):
bank_machines.append(bank_machine)
self.submodules += bank_machine
self.comb += getattr(self.interface, "bank"+str(i)).connect(bank_machine.req)
# FIXME: simulation workaround
if phy_settings.memtype == "DDR3" and phy_settings.nphases == 2:
self.comb += bank_machine.req.adr[-1].eq(0)
self.submodules.multiplexer = Multiplexer(settings,
bank_machines,