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frontend/wishbone: round port_data_width to lowest power of 2 (required for ECC cases)

This commit is contained in:
Florent Kermarrec 2020-02-10 09:56:36 +01:00
parent ad173d69fb
commit ca17cfd83d
1 changed files with 3 additions and 1 deletions
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4
litedram/frontend/wishbone.py
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@ -3,6 +3,8 @@
"""Wishbone frontend for LiteDRAM""" """Wishbone frontend for LiteDRAM"""
from math import log2
from migen import * from migen import *
from litex.soc.interconnect import stream from litex.soc.interconnect import stream
@ -13,7 +15,7 @@ from litex.soc.interconnect import stream
class LiteDRAMWishbone2Native(Module): class LiteDRAMWishbone2Native(Module):
def __init__(self, wishbone, port, base_address=0x00000000): def __init__(self, wishbone, port, base_address=0x00000000):
wishbone_data_width = len(wishbone.dat_w) wishbone_data_width = len(wishbone.dat_w)
port_data_width = len(port.wdata.data) port_data_width = 2**int(log2(len(port.wdata.data))) # Round to lowest power 2
assert wishbone_data_width >= port_data_width assert wishbone_data_width >= port_data_width
# # # # # #