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frontend/wishbone: add LiteDRAMWishbone2AXI

This commit is contained in:
Florent Kermarrec 2018-11-09 15:32:49 +01:00
parent 3586e157f2
commit ca82ac18d0
1 changed files with 52 additions and 0 deletions
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52
litedram/frontend/wishbone.py
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@ -48,3 +48,55 @@ class LiteDRAMWishbone2Native(Module):
port.wdata.data.eq(wishbone.dat_w),
wishbone.dat_r.eq(port.rdata.data)
]
class LiteDRAMWishbone2AXI(Module):
def __init__(self, wishbone, port):
# # #
ashift = log2_int(port.data_width//8)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(wishbone.cyc & wishbone.stb,
If(wishbone.we,
NextValue(port.aw.valid, 1),
NextValue(port.w.valid, 1),
NextState("WRITE")
).Else(
NextValue(port.ar.valid, 1),
NextState("READ")
)
)
)
fsm.act("WRITE",
port.aw.addr[ashift:].eq(wishbone.adr),
port.w.last.eq(1),
port.w.data.eq(wishbone.dat_w),
port.w.strb.eq(wishbone.sel),
If(port.aw.ready,
NextValue(port.aw.valid, 0)
),
If(port.w.ready,
NextValue(port.w.valid, 0)
),
If(port.b.valid,
port.b.ready.eq(1),
wishbone.ack.eq(1),
wishbone.err.eq(port.b.resp != 0b00),
NextState("IDLE")
)
)
fsm.act("READ",
port.ar.addr[ashift:].eq(wishbone.adr),
If(port.ar.ready,
NextValue(port.ar.valid, 0)
),
If(port.r.valid,
port.r.ready.eq(1),
wishbone.dat_r.eq(port.r.data),
wishbone.ack.eq(1),
wishbone.err.eq(port.r.resp != 0b10),
NextState("IDLE")
)
)