frontend/adapter: Add early_cmd_ready parameter to keep default behaviour to False but allow enabling it in Avalon Frontend.
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1b7435c6d5
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@ -70,7 +70,7 @@ class LiteDRAMNativePortDownConverter(Module):
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- A read from the user generates N reads to the controller and returned
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- A read from the user generates N reads to the controller and returned
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datas are regrouped in a single data presented to the user.
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datas are regrouped in a single data presented to the user.
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"""
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"""
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def __init__(self, port_from, port_to, reverse=False):
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def __init__(self, port_from, port_to, reverse=False, early_cmd_ready=False):
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assert port_from.clock_domain == port_to.clock_domain
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assert port_from.clock_domain == port_to.clock_domain
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assert port_from.data_width > port_to.data_width
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assert port_from.data_width > port_to.data_width
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assert port_from.mode == port_to.mode
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assert port_from.mode == port_to.mode
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@ -88,7 +88,7 @@ class LiteDRAMNativePortDownConverter(Module):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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fsm.act("IDLE",
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port_from.cmd.ready.eq(1),
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port_from.cmd.ready.eq(early_cmd_ready),
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If(port_from.cmd.valid,
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If(port_from.cmd.valid,
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NextValue(cmd_count, 0),
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NextValue(cmd_count, 0),
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NextValue(cmd_addr, port_from.cmd.addr),
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NextValue(cmd_addr, port_from.cmd.addr),
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@ -103,6 +103,7 @@ class LiteDRAMNativePortDownConverter(Module):
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If(port_to.cmd.ready,
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If(port_to.cmd.ready,
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NextValue(cmd_count, cmd_count + 1),
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NextValue(cmd_count, cmd_count + 1),
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If(cmd_count == (ratio - 1),
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If(cmd_count == (ratio - 1),
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port_from.cmd.ready.eq(~early_cmd_ready),
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NextState("IDLE")
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NextState("IDLE")
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)
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)
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)
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)
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@ -362,7 +363,7 @@ class LiteDRAMNativePortUpConverter(Module):
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# LiteDRAMNativePortConverter ----------------------------------------------------------------------
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# LiteDRAMNativePortConverter ----------------------------------------------------------------------
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class LiteDRAMNativePortConverter(Module):
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class LiteDRAMNativePortConverter(Module):
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def __init__(self, port_from, port_to, reverse=False):
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def __init__(self, port_from, port_to, reverse=False, early_cmd_ready=False):
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assert port_from.clock_domain == port_to.clock_domain
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assert port_from.clock_domain == port_to.clock_domain
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assert port_from.mode == port_to.mode
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assert port_from.mode == port_to.mode
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@ -372,7 +373,7 @@ class LiteDRAMNativePortConverter(Module):
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if ratio > 1:
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if ratio > 1:
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# DownConverter
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# DownConverter
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self.submodules.converter = LiteDRAMNativePortDownConverter(port_from, port_to, reverse)
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self.submodules.converter = LiteDRAMNativePortDownConverter(port_from, port_to, reverse, early_cmd_ready)
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elif ratio < 1:
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elif ratio < 1:
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# UpConverter
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# UpConverter
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self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse)
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self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse)
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@ -44,7 +44,7 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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address_width = port.address_width + addr_shift,
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address_width = port.address_width + addr_shift,
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data_width = avalon_data_width
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data_width = avalon_data_width
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)
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)
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self.converter = LiteDRAMNativePortConverter(new_port, port)
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self.converter = LiteDRAMNativePortConverter(new_port, port, early_cmd_ready=True)
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port = new_port
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port = new_port
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# # #
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# # #
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