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s7ddrphy/usddrphy: add cmd_delay parameter and pass cmd_latency/cmd_delay to PhySettings/Software.

This commit is contained in:
Florent Kermarrec 2020-09-07 18:50:01 +02:00
parent 3bab6f2024
commit cf45ca48bc
4 changed files with 13 additions and 2 deletions
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3
litedram/common.py
View File

@ -176,7 +176,8 @@ class PhySettings(Settings):
nphases, nphases,
rdphase, wrphase, rdphase, wrphase,
rdcmdphase, wrcmdphase, rdcmdphase, wrcmdphase,
cl, read_latency, write_latency, nranks=1, cwl=None): cl, read_latency, write_latency, nranks=1, cwl=None,
cmd_latency=None, cmd_delay=None):
self.set_attributes(locals()) self.set_attributes(locals())
self.cwl = cl if cwl is None else cwl self.cwl = cl if cwl is None else cwl
self.is_rdimm = False self.is_rdimm = False

4
litedram/init.py
View File

@ -485,6 +485,10 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
r += "#define SDRAM_PHY_XDR "+str(1 if phy_settings.memtype == "SDR" else 2) + "\n" r += "#define SDRAM_PHY_XDR "+str(1 if phy_settings.memtype == "SDR" else 2) + "\n"
r += "#define SDRAM_PHY_DATABITS "+str(phy_settings.databits) + "\n" r += "#define SDRAM_PHY_DATABITS "+str(phy_settings.databits) + "\n"
r += "#define SDRAM_PHY_PHASES "+str(nphases)+"\n" r += "#define SDRAM_PHY_PHASES "+str(nphases)+"\n"
if phy_settings.cmd_latency is not None:
r += "#define SDRAM_PHY_CMD_LATENCY "+str(phy_settings.cmd_latency)+"\n"
if phy_settings.cmd_delay is not None:
r += "#define SDRAM_PHY_CMD_DELAY "+str(phy_settings.cmd_delay)+"\n"
# Define Read/Write Leveling capability # Define Read/Write Leveling capability
if phytype in ["USDDRPHY", "USPDDRPHY", "K7DDRPHY", "V7DDRPHY"]: if phytype in ["USDDRPHY", "USPDDRPHY", "K7DDRPHY", "V7DDRPHY"]:

3
litedram/phy/s7ddrphy.py
View File

@ -27,6 +27,7 @@ class S7DDRPHY(Module, AutoCSR):
sys_clk_freq = 100e6, sys_clk_freq = 100e6,
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6,
cmd_latency = 0, cmd_latency = 0,
cmd_delay = None,
interface_type = "NETWORKING"): interface_type = "NETWORKING"):
assert not (memtype == "DDR3" and nphases == 2) assert not (memtype == "DDR3" and nphases == 2)
assert interface_type in ["NETWORKING", "MEMORY"] assert interface_type in ["NETWORKING", "MEMORY"]
@ -101,6 +102,8 @@ class S7DDRPHY(Module, AutoCSR):
cwl = cwl - cmd_latency, cwl = cwl - cmd_latency,
read_latency = 2 + cl_sys_latency + iserdese2_latency[interface_type] + 2, read_latency = 2 + cl_sys_latency + iserdese2_latency[interface_type] + 2,
write_latency = cwl_sys_latency, write_latency = cwl_sys_latency,
cmd_latency = cmd_latency,
cmd_delay = cmd_delay,
) )
# DFI Interface ---------------------------------------------------------------------------- # DFI Interface ----------------------------------------------------------------------------

5
litedram/phy/usddrphy.py
View File

@ -26,6 +26,7 @@ class USDDRPHY(Module, AutoCSR):
sys_clk_freq = 100e6, sys_clk_freq = 100e6,
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6,
cmd_latency = 1, cmd_latency = 1,
cmd_delay = None,
is_rdimm = False): is_rdimm = False):
phytype = self.__class__.__name__ phytype = self.__class__.__name__
device = {"USDDRPHY": "ULTRASCALE", "USPDDRPHY": "ULTRASCALE_PLUS"}[phytype] device = {"USDDRPHY": "ULTRASCALE", "USPDDRPHY": "ULTRASCALE_PLUS"}[phytype]
@ -93,7 +94,9 @@ class USDDRPHY(Module, AutoCSR):
cl = cl, cl = cl,
cwl = cwl - cmd_latency, cwl = cwl - cmd_latency,
read_latency = 2 + cl_sys_latency + 1 + 2, read_latency = 2 + cl_sys_latency + 1 + 2,
write_latency = cwl_sys_latency write_latency = cwl_sys_latency,
cmd_latency = cmd_latency,
cmd_delay = cmd_delay,
) )
if is_rdimm: if is_rdimm: