Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

test/reference: update.

This commit is contained in:
Florent Kermarrec 2020-04-16 11:38:43 +02:00
parent 45a03dff53
commit d061e60611
3 changed files with 23 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
test/reference/ddr3_init.h
View File

@ -4,7 +4,13 @@
#include <generated/csr.h> #include <generated/csr.h>
#include <hw/flags.h> #include <hw/flags.h>
#define DFII_NPHASES 4 #define SDRAM_PHY_K7DDRPHY
#define SDRAM_PHY_PHASES 4
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
#define SDRAM_PHY_READ_LEVELING_CAPABLE
#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
#define SDRAM_PHY_DELAYS 32
#define SDRAM_PHY_BITSLIPS 8
static void cdelay(int i); static void cdelay(int i);
@ -39,14 +45,14 @@ __attribute__((unused)) static void command_p3(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[DFII_NPHASES] = { const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
CSR_SDRAM_DFII_PI0_WRDATA_ADDR, CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
CSR_SDRAM_DFII_PI1_WRDATA_ADDR, CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
CSR_SDRAM_DFII_PI2_WRDATA_ADDR, CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
CSR_SDRAM_DFII_PI3_WRDATA_ADDR CSR_SDRAM_DFII_PI3_WRDATA_ADDR
}; };
const unsigned long sdram_dfii_pix_rddata_addr[DFII_NPHASES] = { const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
CSR_SDRAM_DFII_PI0_RDDATA_ADDR, CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
CSR_SDRAM_DFII_PI1_RDDATA_ADDR, CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
CSR_SDRAM_DFII_PI2_RDDATA_ADDR, CSR_SDRAM_DFII_PI2_RDDATA_ADDR,

13
test/reference/ddr4_init.h
View File

@ -4,7 +4,14 @@
#include <generated/csr.h> #include <generated/csr.h>
#include <hw/flags.h> #include <hw/flags.h>
#define DFII_NPHASES 4 #define SDRAM_PHY_USDDRPHY
#define SDRAM_PHY_PHASES 4
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
#define SDRAM_PHY_WRITE_LEVELING_REINIT
#define SDRAM_PHY_READ_LEVELING_CAPABLE
#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
#define SDRAM_PHY_DELAYS 512
#define SDRAM_PHY_BITSLIPS 8
static void cdelay(int i); static void cdelay(int i);
@ -39,14 +46,14 @@ __attribute__((unused)) static void command_p3(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[DFII_NPHASES] = { const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
CSR_SDRAM_DFII_PI0_WRDATA_ADDR, CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
CSR_SDRAM_DFII_PI1_WRDATA_ADDR, CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
CSR_SDRAM_DFII_PI2_WRDATA_ADDR, CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
CSR_SDRAM_DFII_PI3_WRDATA_ADDR CSR_SDRAM_DFII_PI3_WRDATA_ADDR
}; };
const unsigned long sdram_dfii_pix_rddata_addr[DFII_NPHASES] = { const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
CSR_SDRAM_DFII_PI0_RDDATA_ADDR, CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
CSR_SDRAM_DFII_PI1_RDDATA_ADDR, CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
CSR_SDRAM_DFII_PI2_RDDATA_ADDR, CSR_SDRAM_DFII_PI2_RDDATA_ADDR,

7
test/reference/sdr_init.h
View File

@ -4,7 +4,8 @@
#include <generated/csr.h> #include <generated/csr.h>
#include <hw/flags.h> #include <hw/flags.h>
#define DFII_NPHASES 1 #define SDRAM_PHY_GENSDRPHY
#define SDRAM_PHY_PHASES 1
static void cdelay(int i); static void cdelay(int i);
@ -24,11 +25,11 @@ __attribute__((unused)) static void command_p0(int cmd)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[DFII_NPHASES] = { const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
CSR_SDRAM_DFII_PI0_WRDATA_ADDR CSR_SDRAM_DFII_PI0_WRDATA_ADDR
}; };
const unsigned long sdram_dfii_pix_rddata_addr[DFII_NPHASES] = { const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
CSR_SDRAM_DFII_PI0_RDDATA_ADDR CSR_SDRAM_DFII_PI0_RDDATA_ADDR
}; };