phy/usddrphy: simplify dq_bitslip.o mapping.
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@ -421,18 +421,8 @@ class USDDRPHY(Module, AutoCSR):
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io_IO = pads.dq[i],
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io_IO = pads.dq[i],
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)
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)
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]
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]
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for n in range(8):
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self.comb += [
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self.comb += dfi.phases[n//2].rddata[n%2*databits+i].eq(dq_bitslip.o[n])
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dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]),
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dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]),
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dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]),
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dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]),
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dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]),
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dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]),
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dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]),
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dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7]),
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]
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# Read Control Path ------------------------------------------------------------------------
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# Read Control Path ------------------------------------------------------------------------
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# Creates a shift register of read commands coming from the DFI interface. This shift register
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# Creates a shift register of read commands coming from the DFI interface. This shift register
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