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Merge pull request #320 from antmicro/msieron/sdram-spd 

init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`
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enjoy-digital 2023-01-10 09:39:12 +01:00 committed by GitHub
parent 8339f54322 8fa325310a
commit d17b021aa2
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1 changed files with 8 additions and 1 deletions
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litedram/init.py
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@ -875,7 +875,7 @@ class CGenerator(list):
self.append("}") self.append("}")
def get_sdram_phy_c_header(phy_settings, timing_settings): def get_sdram_phy_c_header(phy_settings, timing_settings, geom_settings):
r = CGenerator() r = CGenerator()
r.header_guard("__GENERATED_SDRAM_PHY_H") r.header_guard("__GENERATED_SDRAM_PHY_H")
r.include("<hw/common.h>") r.include("<hw/common.h>")
@ -937,10 +937,17 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
if phy_settings.bitslips > 0: if phy_settings.bitslips > 0:
r.define("SDRAM_PHY_BITSLIPS", phy_settings.bitslips) r.define("SDRAM_PHY_BITSLIPS", phy_settings.bitslips)
r.define(f"SDRAM_PHY_{phy_settings.memtype}")
if phy_settings.is_rdimm: if phy_settings.is_rdimm:
assert phy_settings.memtype == "DDR4" assert phy_settings.memtype == "DDR4"
r.define("SDRAM_PHY_DDR4_RDIMM") r.define("SDRAM_PHY_DDR4_RDIMM")
# litedram doesn't support multiple ranks
supported_memory = 2 ** (geom_settings.bankbits +
geom_settings.rowbits +
geom_settings.colbits) * phy_settings.databits // 8
r.define("SDRAM_PHY_SUPPORTED_MEMORY", f"0x{supported_memory:016x}ULL")
r.newline() r.newline()
r += "void cdelay(int i);" r += "void cdelay(int i);"