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phy/gensdrphy: compute default cl from sys_clk_freq (similar what is already done on other PHYs).

This commit is contained in:
Florent Kermarrec 2021-01-04 11:29:53 +01:00
parent e683b48c4a
commit d4c5c7cef8
2 changed files with 16 additions and 6 deletions
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8
litedram/common.py
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@ -28,7 +28,10 @@ burst_lengths = {
def get_default_cl_cwl(memtype, tck): def get_default_cl_cwl(memtype, tck):
f_to_cl_cwl = OrderedDict() f_to_cl_cwl = OrderedDict()
if memtype == "DDR2": if memtype == "SDR":
f_to_cl_cwl[100e6] = (2, None)
f_to_cl_cwl[133e6] = (3, None)
elif memtype == "DDR2":
f_to_cl_cwl[400e6] = (3, 2) f_to_cl_cwl[400e6] = (3, 2)
f_to_cl_cwl[533e6] = (4, 3) f_to_cl_cwl[533e6] = (4, 3)
f_to_cl_cwl[677e6] = (5, 4) f_to_cl_cwl[677e6] = (5, 4)
@ -49,7 +52,8 @@ def get_default_cl_cwl(memtype, tck):
else: else:
raise ValueError raise ValueError
for f, (cl, cwl) in f_to_cl_cwl.items(): for f, (cl, cwl) in f_to_cl_cwl.items():
if tck >= 2/f: m = 2 if "DDR" in memtype else 1
if tck >= m/f:
return cl, cwl return cl, cwl
raise ValueError raise ValueError

14
litedram/phy/gensdrphy.py
View File

@ -17,15 +17,17 @@ from litedram.phy.dfi import *
# Generic SDR PHY ---------------------------------------------------------------------------------- # Generic SDR PHY ----------------------------------------------------------------------------------
class GENSDRPHY(Module): class GENSDRPHY(Module):
def __init__(self, pads, cl=2): def __init__(self, pads, sys_clk_freq=100e6, cl=None):
pads = PHYPadsCombiner(pads) pads = PHYPadsCombiner(pads)
addressbits = len(pads.a) addressbits = len(pads.a)
bankbits = len(pads.ba) bankbits = len(pads.ba)
nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n) nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
databits = len(pads.dq) databits = len(pads.dq)
assert cl in [2, 3]
assert databits%8 == 0 assert databits%8 == 0
# Parameters -------------------------------------------------------------------------------
cl = get_default_cl(memtype="SDR", tck=1/sys_clk_freq) if cl is None else cl
# PHY settings ----------------------------------------------------------------------------- # PHY settings -----------------------------------------------------------------------------
self.settings = PhySettings( self.settings = PhySettings(
phytype = "GENSDRPHY", phytype = "GENSDRPHY",
@ -85,7 +87,7 @@ class GENSDRPHY(Module):
# Half-rate Generic SDR PHY ------------------------------------------------------------------------ # Half-rate Generic SDR PHY ------------------------------------------------------------------------
class HalfRateGENSDRPHY(Module): class HalfRateGENSDRPHY(Module):
def __init__(self, pads, cl=2): def __init__(self, pads, sys_clk_freq=100e6, cl=None):
pads = PHYPadsCombiner(pads) pads = PHYPadsCombiner(pads)
addressbits = len(pads.a) addressbits = len(pads.a)
bankbits = len(pads.ba) bankbits = len(pads.ba)
@ -93,8 +95,12 @@ class HalfRateGENSDRPHY(Module):
databits = len(pads.dq) databits = len(pads.dq)
nphases = 2 nphases = 2
# Parameters -------------------------------------------------------------------------------
cl = get_default_cl(memtype="SDR", tck=1/sys_clk_freq) if cl is None else cl
# FullRate PHY ----------------------------------------------------------------------------- # FullRate PHY -----------------------------------------------------------------------------
full_rate_phy = GENSDRPHY(pads, cl) full_rate_phy = GENSDRPHY(pads, 2*sys_clk_freq, cl)
self.submodules += ClockDomainsRenamer("sys2x")(full_rate_phy) self.submodules += ClockDomainsRenamer("sys2x")(full_rate_phy)
# Clocking --------------------------------------------------------------------------------- # Clocking ---------------------------------------------------------------------------------